/[dynamips]/trunk/ppc32.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.7-RC1/ppc32.h revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC upstream/dynamips-0.2.7/ppc32.h revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC
# Line 26  Line 26 
26  #define PPC32_MIN_PAGE_IMASK   (PPC32_MIN_PAGE_SIZE - 1)  #define PPC32_MIN_PAGE_IMASK   (PPC32_MIN_PAGE_SIZE - 1)
27  #define PPC32_MIN_PAGE_MASK    0xFFFFF000  #define PPC32_MIN_PAGE_MASK    0xFFFFF000
28    
29    /* Number of instructions per page */
30    #define PPC32_INSN_PER_PAGE    (PPC32_MIN_PAGE_SIZE/sizeof(ppc_insn_t))
31    
32  /* Starting point for ROM */  /* Starting point for ROM */
33  #define PPC32_ROM_START  0xfff00100  #define PPC32_ROM_START  0xfff00100
34  #define PPC32_ROM_SP     0x00006000  #define PPC32_ROM_SP     0x00006000
# Line 68  Line 71 
71  #define PPC32_EXC_TRACE     0x00000D00   /* Trace */  #define PPC32_EXC_TRACE     0x00000D00   /* Trace */
72  #define PPC32_EXC_FPU_HLP   0x00000E00   /* Floating-Point Assist */  #define PPC32_EXC_FPU_HLP   0x00000E00   /* Floating-Point Assist */
73    
74    /* Condition Register (CR) is accessed through 8 fields of 4 bits */
75    #define ppc32_get_cr_field(n)  ((n) >> 2)
76    #define ppc32_get_cr_bit(n)    (~(n) & 0x03)
77    
78    /* Positions of LT, GT, EQ and SO bits in CR fields */
79    #define PPC32_CR_LT_BIT  3
80    #define PPC32_CR_GT_BIT  2
81    #define PPC32_CR_EQ_BIT  1
82    #define PPC32_CR_SO_BIT  0
83    
84  /* CR0 (Condition Register Field 0) bits */  /* CR0 (Condition Register Field 0) bits */
85  #define PPC32_CR0_LT_BIT    31  #define PPC32_CR0_LT_BIT    31
86  #define PPC32_CR0_LT        (1 << PPC32_CR0_LT_BIT)   /* Negative */  #define PPC32_CR0_LT        (1 << PPC32_CR0_LT_BIT)   /* Negative */
# Line 281  struct cpu_ppc { Line 294  struct cpu_ppc {
294     volatile m_uint32_t irq_pending,irq_check;     volatile m_uint32_t irq_pending,irq_check;
295    
296     /* XER, Condition Register, Link Register, Count Register */     /* XER, Condition Register, Link Register, Count Register */
297     m_uint32_t xer,cr,lr,ctr,reserve;     m_uint32_t xer,lr,ctr,reserve;
298     m_uint32_t xer_ca;     m_uint32_t xer_ca;
299    
300       /* Condition Register (CR) fields */
301       u_int cr_fields[8];
302    
303     /* MTS caches (Instruction+Data) */     /* MTS caches (Instruction+Data) */
304     mts32_entry_t *mts_cache[2];     mts32_entry_t *mts_cache[2];
305    
306     /* Code page translation cache */     /* Code page translation cache and physical page mapping */
307     ppc32_jit_tcb_t **exec_phys_map;     ppc32_jit_tcb_t **exec_blk_map,**exec_phys_map;
308    
309     /* Virtual address to physical page translation */     /* Virtual address to physical page translation */
310     fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid,     fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid,
# Line 391  struct cpu_ppc { Line 407  struct cpu_ppc {
407     /* Fast memory operations use */     /* Fast memory operations use */
408     u_int fast_memop;     u_int fast_memop;
409    
410     /* IRQ idling preemption */     /* Direct block jump */
411     u_int irq_idle_preempt[32];     u_int exec_blk_direct_jump;
412    
413     /* Current exec page (non-JIT) info */     /* Current exec page (non-JIT) info */
414     m_uint64_t njm_exec_page;     m_uint64_t njm_exec_page;
# Line 407  struct cpu_ppc { Line 423  struct cpu_ppc {
423     /* Breakpoints */     /* Breakpoints */
424     m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];     m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];
425     u_int breakpoints_enabled;     u_int breakpoints_enabled;
426    
427       /* JIT host register allocation */
428       char *jit_hreg_seq_name;
429       int ppc_reg_map[PPC32_GPR_NR];
430       struct hreg_map *hreg_map_list,*hreg_lru;
431       struct hreg_map hreg_map[JIT_HOST_NREG];
432  };  };
433    
434    #define PPC32_CR_FIELD_OFFSET(f) \
435       (OFFSET(cpu_ppc_t,cr_fields)+((f) * sizeof(u_int)))
436    
437    /* Get the full CR register */
438    static forced_inline m_uint32_t ppc32_get_cr(cpu_ppc_t *cpu)
439    {
440       m_uint32_t cr = 0;
441       int i;
442    
443       for(i=0;i<8;i++)
444          cr |= cpu->cr_fields[i] << (28 - (i << 2));
445    
446       return(cr);
447    }
448    
449    /* Set the CR fields given a CR value */
450    static forced_inline void ppc32_set_cr(cpu_ppc_t *cpu,m_uint32_t cr)
451    {
452       int i;
453    
454       for(i=0;i<8;i++)
455          cpu->cr_fields[i] = (cr >> (28 - (i << 2))) & 0x0F;
456    }
457    
458    /* Get a CR bit */
459    static forced_inline m_uint32_t ppc32_read_cr_bit(cpu_ppc_t *cpu,u_int bit)
460    {
461       m_uint32_t res;
462    
463       res = cpu->cr_fields[ppc32_get_cr_field(bit)] >> ppc32_get_cr_bit(bit);
464       return(res & 0x01);
465    }
466    
467    /* Set a CR bit */
468    static forced_inline void ppc32_set_cr_bit(cpu_ppc_t *cpu,u_int bit)
469    {
470       cpu->cr_fields[ppc32_get_cr_field(bit)] |= 1 << ppc32_get_cr_bit(bit);
471    }
472    
473    /* Clear a CR bit */
474    static forced_inline void ppc32_clear_cr_bit(cpu_ppc_t *cpu,u_int bit)
475    {
476       cpu->cr_fields[ppc32_get_cr_field(bit)] &= ~(1 << ppc32_get_cr_bit(bit));
477    }
478    
479  /* Reset a PowerPC CPU */  /* Reset a PowerPC CPU */
480  int ppc32_reset(cpu_ppc_t *cpu);  int ppc32_reset(cpu_ppc_t *cpu);
481    
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