/[dynamips]/trunk/nojit_trans.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/nojit_trans.h

Parent Directory Parent Directory | Revision Log Revision Log


Revision 12 - (show annotations)
Sat Oct 6 16:45:40 2007 UTC (11 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 1333 byte(s)
make working copy

1 /*
2 * Cisco 7200 (Predator) simulation platform.
3 * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
4 *
5 * Just an empty JIT template file for architectures not supported by the JIT
6 * code.
7 */
8
9 #ifndef __NOJIT_TRANS_H__
10 #define __NOJIT_TRANS_H__
11
12 #include "utils.h"
13 #include "mips64.h"
14 #include "dynamips.h"
15 #include "cp0.h"
16
17 #define JIT_SUPPORT 0
18
19 #define insn_block_set_patch(a,b)
20 #define insn_block_set_jump(a,b)
21
22 /* MIPS instruction array */
23 extern struct insn_tag mips64_insn_tags[];
24
25 /* Push epilog for an x86 instruction block */
26 void insn_block_push_epilog(insn_block_t *block);
27
28 /* Execute JIT code */
29 void insn_block_exec_jit_code(cpu_mips_t *cpu,insn_block_t *block);
30
31 /* Set the Pointer Counter (PC) register */
32 void mips64_set_pc(insn_block_t *b,m_uint64_t new_pc);
33
34 /* Set the Return Address (RA) register */
35 void mips64_set_ra(insn_block_t *b,m_uint64_t ret_pc);
36
37 /* Virtual Breakpoint */
38 void mips64_emit_breakpoint(insn_block_t *b);
39
40 /* Emit unhandled instruction code */
41 int mips64_emit_invalid_delay_slot(insn_block_t *b);
42
43 /*
44 * Increment count register and trigger the timer IRQ if value in compare
45 * register is the same.
46 */
47 void mips64_inc_cp0_count_reg(insn_block_t *b);
48
49 /* Increment the number of executed instructions (performance debugging) */
50 void mips64_inc_perf_counter(insn_block_t *b);
51
52 #endif

  ViewVC Help
Powered by ViewVC 1.1.26