/[dynamips]/trunk/mips64_x86_trans.c
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Diff of /trunk/mips64_x86_trans.c

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upstream/dynamips-0.2.7/mips64_x86_trans.c revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC upstream/dynamips-0.2.8-RC1/mips64_x86_trans.c revision 11 by dpavlin, Sat Oct 6 16:33:40 2007 UTC
# Line 227  static void mips64_emit_memop_fast64(mip Line 227  static void mips64_emit_memop_fast64(mip
227                                       memop_fast_access op_handler)                                       memop_fast_access op_handler)
228  {  {
229     m_uint64_t val = sign_extend(offset,16);     m_uint64_t val = sign_extend(offset,16);
230     u_char *test1,*test2,*test3,*p_exception,*p_exit;     u_char *test1,*test2,*test3,*p_exit;
231    
232     test3 = NULL;     test3 = NULL;
233    
# Line 310  static void mips64_emit_memop_fast64(mip Line 310  static void mips64_emit_memop_fast64(mip
310     x86_call_membase(b->jit_ptr,X86_EDI,MEMOP_OFFSET(opcode));     x86_call_membase(b->jit_ptr,X86_EDI,MEMOP_OFFSET(opcode));
311     x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);     x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);
312    
    /* Check for exception */  
    x86_test_reg_reg(b->jit_ptr,X86_EAX,X86_EAX);  
    p_exception = b->jit_ptr;  
    x86_branch8(b->jit_ptr, X86_CC_Z, 0, 1);  
    mips64_jit_tcb_push_epilog(b);  
   
313     x86_patch(p_exit,b->jit_ptr);     x86_patch(p_exit,b->jit_ptr);
    x86_patch(p_exception,b->jit_ptr);  
314  }  }
315    
316  /* Fast memory operation (32-bit) */  /* Fast memory operation (32-bit) */
# Line 327  static void mips64_emit_memop_fast32(mip Line 320  static void mips64_emit_memop_fast32(mip
320                                       memop_fast_access op_handler)                                       memop_fast_access op_handler)
321  {  {
322     m_uint32_t val = sign_extend(offset,16);     m_uint32_t val = sign_extend(offset,16);
323     u_char *test1,*test2,*p_exception,*p_exit;     u_char *test1,*test2,*p_exit;
324    
325     test2 = NULL;     test2 = NULL;
326    
# Line 405  static void mips64_emit_memop_fast32(mip Line 398  static void mips64_emit_memop_fast32(mip
398     x86_call_membase(b->jit_ptr,X86_EDI,MEMOP_OFFSET(opcode));     x86_call_membase(b->jit_ptr,X86_EDI,MEMOP_OFFSET(opcode));
399     x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);     x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);
400    
    /* Check for exception */  
    x86_test_reg_reg(b->jit_ptr,X86_EAX,X86_EAX);  
    p_exception = b->jit_ptr;  
    x86_branch8(b->jit_ptr, X86_CC_Z, 0, 1);  
    mips64_jit_tcb_push_epilog(b);  
   
401     x86_patch(p_exit,b->jit_ptr);     x86_patch(p_exit,b->jit_ptr);
    x86_patch(p_exception,b->jit_ptr);  
402  }  }
403    
404  /* Fast memory operation */  /* Fast memory operation */
# Line 439  static void mips64_emit_memop(mips64_jit Line 425  static void mips64_emit_memop(mips64_jit
425                                int target,int keep_ll_bit)                                int target,int keep_ll_bit)
426  {  {
427     m_uint64_t val = sign_extend(offset,16);     m_uint64_t val = sign_extend(offset,16);
    u_char *test1;  
428    
429     /* Save PC for exception handling */     /* Save PC for exception handling */
430     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
# Line 471  static void mips64_emit_memop(mips64_jit Line 456  static void mips64_emit_memop(mips64_jit
456     x86_push_reg(b->jit_ptr,X86_EBX);     x86_push_reg(b->jit_ptr,X86_EBX);
457     x86_call_membase(b->jit_ptr,X86_EDI,MEMOP_OFFSET(op));     x86_call_membase(b->jit_ptr,X86_EDI,MEMOP_OFFSET(op));
458     x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);     x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);
   
    /* Exception ? */  
    x86_test_reg_reg(b->jit_ptr,X86_EAX,X86_EAX);  
    test1 = b->jit_ptr;  
    x86_branch8(b->jit_ptr, X86_CC_Z, 0, 1);  
    mips64_jit_tcb_push_epilog(b);  
    x86_patch(test1,b->jit_ptr);  
459  }  }
460    
461  /* Coprocessor Register transfert operation */  /* Coprocessor Register transfert operation */
# Line 501  static void mips64_emit_cp_xfr_op(mips64 Line 479  static void mips64_emit_cp_xfr_op(mips64
479  /* Virtual Breakpoint */  /* Virtual Breakpoint */
480  void mips64_emit_breakpoint(mips64_jit_tcb_t *b)  void mips64_emit_breakpoint(mips64_jit_tcb_t *b)
481  {  {
482       x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);
483     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);
484     mips64_emit_c_call(b,mips64_run_breakpoint);     mips64_emit_c_call(b,mips64_run_breakpoint);
485       x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);
486  }  }
487    
488  /* Unknown opcode handler */  /* Unknown opcode handler */
# Line 542  static fastcall void mips64_invalid_dela Line 522  static fastcall void mips64_invalid_dela
522  /* Emit unhandled instruction code */  /* Emit unhandled instruction code */
523  int mips64_emit_invalid_delay_slot(mips64_jit_tcb_t *b)  int mips64_emit_invalid_delay_slot(mips64_jit_tcb_t *b)
524  {    {  
525       x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);
526     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);
527     mips64_emit_c_call(b,mips64_invalid_delay_slot);     mips64_emit_c_call(b,mips64_invalid_delay_slot);
528       x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);
529      
530     mips64_jit_tcb_push_epilog(b);     mips64_jit_tcb_push_epilog(b);
531     return(0);     return(0);
532  }  }
533    
 /* Located in external assembly module */  
 #ifdef FAST_ASM  
 extern void mips64_inc_cp0_cnt_asm(void);  
 #endif  
   
534  /*  /*
535   * Increment count register and trigger the timer IRQ if value in compare   * Increment count register and trigger the timer IRQ if value in compare
536   * register is the same.   * register is the same.
# Line 560  extern void mips64_inc_cp0_cnt_asm(void) Line 538  extern void mips64_inc_cp0_cnt_asm(void)
538  void mips64_inc_cp0_count_reg(mips64_jit_tcb_t *b)  void mips64_inc_cp0_count_reg(mips64_jit_tcb_t *b)
539  {  {
540     x86_inc_membase(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,cp0_virt_cnt_reg));     x86_inc_membase(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,cp0_virt_cnt_reg));
   
 #if 0 /* TIMER_IRQ */  
 #ifdef FAST_ASM  
    mips64_emit_basic_c_call(b,mips64_inc_cp0_cnt_asm);  
 #else  
    x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);  
    mips64_emit_basic_c_call(b,mips64_exec_inc_cp0_cnt);  
 #endif  
 #endif  
541  }  }
542    
543  /* Check if there are pending IRQ */  /* Check if there are pending IRQ */
# Line 597  void mips64_check_pending_irq(mips64_jit Line 566  void mips64_check_pending_irq(mips64_jit
566  /* Increment the number of executed instructions (performance debugging) */  /* Increment the number of executed instructions (performance debugging) */
567  void mips64_inc_perf_counter(mips64_jit_tcb_t *b)  void mips64_inc_perf_counter(mips64_jit_tcb_t *b)
568  {  {
569     x86_alu_membase_imm(b->jit_ptr,X86_ADD,     x86_inc_membase(b->jit_ptr,X86_EDI,OFFSET(cpu_mips_t,perf_counter));
                        X86_EDI,OFFSET(cpu_mips_t,perf_counter),1);  
    x86_alu_membase_imm(b->jit_ptr,X86_ADC,  
                        X86_EDI,OFFSET(cpu_mips_t,perf_counter)+4,0);  
570  }  }
571    
572  /* ADD */  /* ADD */
# Line 1421  DECLARE_INSN(BREAK) Line 1387  DECLARE_INSN(BREAK)
1387  {        {      
1388     u_int code = bits(insn,6,25);     u_int code = bits(insn,6,25);
1389    
1390       x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);
1391     x86_mov_reg_imm(b->jit_ptr,X86_EDX,code);     x86_mov_reg_imm(b->jit_ptr,X86_EDX,code);
1392     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);
1393     mips64_emit_basic_c_call(b,mips64_exec_break);     mips64_emit_basic_c_call(b,mips64_exec_break);
1394       x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);
1395    
1396     mips64_jit_tcb_push_epilog(b);     mips64_jit_tcb_push_epilog(b);
1397     return(0);     return(0);
1398  }  }
# Line 2823  DECLARE_INSN(TEQ) Line 2792  DECLARE_INSN(TEQ)
2792     x86_branch8(b->jit_ptr, X86_CC_NE, 0, 1);     x86_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
2793    
2794     /* Generate trap exception */     /* Generate trap exception */
2795       x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);
2796     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);
2797     mips64_emit_c_call(b,mips64_trigger_trap_exception);     mips64_emit_c_call(b,mips64_trigger_trap_exception);
2798       x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);
2799      
2800     mips64_jit_tcb_push_epilog(b);     mips64_jit_tcb_push_epilog(b);
2801    
2802     /* end */     /* end */
# Line 2857  DECLARE_INSN(TEQI) Line 2829  DECLARE_INSN(TEQI)
2829     x86_branch8(b->jit_ptr, X86_CC_NE, 0, 1);     x86_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
2830    
2831     /* Generate trap exception */     /* Generate trap exception */
2832       x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);
2833     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);     x86_mov_reg_reg(b->jit_ptr,X86_EAX,X86_EDI,4);
2834     mips64_emit_c_call(b,mips64_trigger_trap_exception);     mips64_emit_c_call(b,mips64_trigger_trap_exception);
2835       x86_alu_reg_imm(b->jit_ptr,X86_ADD,X86_ESP,12);
2836    
2837     mips64_jit_tcb_push_epilog(b);     mips64_jit_tcb_push_epilog(b);
2838    
2839     /* end */     /* end */
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