/[dynamips]/trunk/mips64_amd64_trans.c
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Annotation of /trunk/mips64_amd64_trans.c

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Revision 12 - (hide annotations)
Sat Oct 6 16:45:40 2007 UTC (16 years, 6 months ago) by dpavlin
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1 dpavlin 7 /*
2     * Cisco router simulation platform.
3     * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4     */
5    
6     #include <stdio.h>
7     #include <stdlib.h>
8     #include <unistd.h>
9     #include <string.h>
10     #include <sys/types.h>
11     #include <sys/stat.h>
12     #include <sys/mman.h>
13     #include <fcntl.h>
14    
15     #include "cpu.h"
16     #include "mips64_jit.h"
17     #include "mips64_amd64_trans.h"
18     #include "mips64_cp0.h"
19     #include "memory.h"
20    
21     /* Macros for CPU structure access */
22     #define REG_OFFSET(reg) (OFFSET(cpu_mips_t,gpr[(reg)]))
23     #define CP0_REG_OFFSET(c0reg) (OFFSET(cpu_mips_t,cp0.reg[(c0reg)]))
24     #define MEMOP_OFFSET(op) (OFFSET(cpu_mips_t,mem_op_fn[(op)]))
25    
26     #define DECLARE_INSN(name) \
27     static int mips64_emit_##name(cpu_mips_t *cpu,mips64_jit_tcb_t *b, \
28     mips_insn_t insn)
29    
30     /* Set an IRQ */
31     void mips64_set_irq(cpu_mips_t *cpu,m_uint8_t irq)
32     {
33     m_uint32_t m;
34     m = (1 << (irq + MIPS_CP0_CAUSE_ISHIFT)) & MIPS_CP0_CAUSE_IMASK;
35     atomic_or(&cpu->irq_cause,m);
36     }
37    
38     /* Clear an IRQ */
39     void mips64_clear_irq(cpu_mips_t *cpu,m_uint8_t irq)
40     {
41     m_uint32_t m;
42     m = (1 << (irq + MIPS_CP0_CAUSE_ISHIFT)) & MIPS_CP0_CAUSE_IMASK;
43     atomic_and(&cpu->irq_cause,~m);
44    
45     if (!cpu->irq_cause)
46     cpu->irq_pending = 0;
47     }
48    
49     /* Load a 64 bit immediate value */
50     static inline void mips64_load_imm(mips64_jit_tcb_t *b,u_int reg,
51     m_uint64_t value)
52     {
53     if (value > 0xffffffffULL)
54     amd64_mov_reg_imm_size(b->jit_ptr,reg,value,8);
55     else
56     amd64_mov_reg_imm(b->jit_ptr,reg,value);
57     }
58    
59     /* Set the Pointer Counter (PC) register */
60     void mips64_set_pc(mips64_jit_tcb_t *b,m_uint64_t new_pc)
61     {
62     mips64_load_imm(b,AMD64_RAX,new_pc);
63     amd64_mov_membase_reg(b->jit_ptr,
64     AMD64_R15,OFFSET(cpu_mips_t,pc),
65     AMD64_RAX,8);
66     }
67    
68     /* Set the Return Address (RA) register */
69     void mips64_set_ra(mips64_jit_tcb_t *b,m_uint64_t ret_pc)
70     {
71     mips64_load_imm(b,AMD64_RAX,ret_pc);
72     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,
73     REG_OFFSET(MIPS_GPR_RA),
74     AMD64_RAX,8);
75     }
76    
77 dpavlin 8 /*
78     * Try to branch directly to the specified JIT block without returning to
79     * main loop.
80     */
81     static void mips64_try_direct_far_jump(cpu_mips_t *cpu,mips64_jit_tcb_t *b,
82     m_uint64_t new_pc)
83     {
84     m_uint64_t new_page;
85     m_uint32_t pc_hash,pc_offset;
86     u_char *test1,*test2,*test3;
87    
88     new_page = new_pc & MIPS_MIN_PAGE_MASK;
89     pc_offset = (new_pc & MIPS_MIN_PAGE_IMASK) >> 2;
90     pc_hash = mips64_jit_get_pc_hash(new_pc);
91    
92     /* Get JIT block info in %rdx */
93     amd64_mov_reg_membase(b->jit_ptr,AMD64_RBX,
94     AMD64_R15,OFFSET(cpu_mips_t,exec_blk_map),8);
95     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,
96     AMD64_RBX,pc_hash*sizeof(void *),8);
97    
98     /* no JIT block found ? */
99     amd64_test_reg_reg(b->jit_ptr,AMD64_RDX,AMD64_RDX);
100     test1 = b->jit_ptr;
101     amd64_branch8(b->jit_ptr, X86_CC_Z, 0, 1);
102    
103     /* Check block IA */
104     mips64_load_imm(b,AMD64_RAX,new_page);
105     amd64_alu_reg_membase_size(b->jit_ptr,X86_CMP,X86_EAX,AMD64_RDX,
106     OFFSET(mips64_jit_tcb_t,start_pc),4);
107     test2 = b->jit_ptr;
108     amd64_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
109    
110     /* Jump to the code */
111     amd64_mov_reg_membase(b->jit_ptr,AMD64_RSI,
112     AMD64_RDX,OFFSET(mips64_jit_tcb_t,jit_insn_ptr),8);
113     amd64_mov_reg_membase(b->jit_ptr,AMD64_RBX,
114     AMD64_RSI,pc_offset * sizeof(void *),8);
115    
116     amd64_test_reg_reg(b->jit_ptr,AMD64_RBX,AMD64_RBX);
117     test3 = b->jit_ptr;
118     amd64_branch8(b->jit_ptr, X86_CC_Z, 0, 1);
119     amd64_jump_reg(b->jit_ptr,AMD64_RBX);
120    
121     /* Returns to caller... */
122     amd64_patch(test1,b->jit_ptr);
123     amd64_patch(test2,b->jit_ptr);
124     amd64_patch(test3,b->jit_ptr);
125    
126     mips64_set_pc(b,new_pc);
127     mips64_jit_tcb_push_epilog(b);
128     }
129    
130 dpavlin 7 /* Set Jump */
131     static void mips64_set_jump(cpu_mips_t *cpu,mips64_jit_tcb_t *b,
132     m_uint64_t new_pc,int local_jump)
133     {
134     int return_to_caller = FALSE;
135     u_char *jump_ptr;
136    
137     if (cpu->sym_trace && !local_jump)
138     return_to_caller = TRUE;
139    
140     if (!return_to_caller && mips64_jit_tcb_local_addr(b,new_pc,&jump_ptr)) {
141     if (jump_ptr) {
142     amd64_jump_code(b->jit_ptr,jump_ptr);
143     } else {
144 dpavlin 8 /* Never jump directly to code in a delay slot */
145     if (mips64_jit_is_delay_slot(b,new_pc)) {
146     mips64_set_pc(b,new_pc);
147     mips64_jit_tcb_push_epilog(b);
148     return;
149     }
150    
151 dpavlin 7 mips64_jit_tcb_record_patch(b,b->jit_ptr,new_pc);
152     amd64_jump32(b->jit_ptr,0);
153     }
154     } else {
155 dpavlin 8 if (cpu->exec_blk_direct_jump) {
156     /* Block lookup optimization */
157     mips64_try_direct_far_jump(cpu,b,new_pc);
158     } else {
159     mips64_set_pc(b,new_pc);
160     mips64_jit_tcb_push_epilog(b);
161     }
162 dpavlin 7 }
163     }
164    
165     /* Basic C call */
166     static forced_inline
167     void mips64_emit_basic_c_call(mips64_jit_tcb_t *b,void *f)
168     {
169     amd64_mov_reg_imm(b->jit_ptr,AMD64_RCX,f);
170     amd64_call_reg(b->jit_ptr,AMD64_RCX);
171     }
172    
173     /* Emit a simple call to a C function without any parameter */
174     static void mips64_emit_c_call(mips64_jit_tcb_t *b,void *f)
175     {
176     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
177     amd64_mov_reg_imm(b->jit_ptr,AMD64_RCX,f);
178     amd64_call_reg(b->jit_ptr,AMD64_RCX);
179     }
180    
181     /* Single-step operation */
182     void mips64_emit_single_step(mips64_jit_tcb_t *b,mips_insn_t insn)
183     {
184     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
185     amd64_mov_reg_imm(b->jit_ptr,AMD64_RSI,insn);
186     mips64_emit_basic_c_call(b,mips64_exec_single_step);
187     }
188    
189     /* Fast memory operation prototype */
190     typedef void (*memop_fast_access)(mips64_jit_tcb_t *b,int target);
191    
192     /* Fast LW */
193     static void mips64_memop_fast_lw(mips64_jit_tcb_t *b,int target)
194     {
195     amd64_mov_reg_memindex(b->jit_ptr,AMD64_RAX,AMD64_RBX,0,AMD64_RSI,0,4);
196     amd64_bswap32(b->jit_ptr,X86_EAX);
197     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EAX);
198    
199     /* Save value in register */
200     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(target),AMD64_RDX,8);
201     }
202    
203     /* Fast SW */
204     static void mips64_memop_fast_sw(mips64_jit_tcb_t *b,int target)
205     {
206     /* Load value from register */
207     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(target),4);
208     amd64_bswap32(b->jit_ptr,X86_EAX);
209     amd64_mov_memindex_reg(b->jit_ptr,AMD64_RBX,0,AMD64_RSI,0,AMD64_RAX,4);
210     }
211    
212     /* Fast memory operation (64-bit) */
213     static void mips64_emit_memop_fast64(mips64_jit_tcb_t *b,int write_op,
214     int opcode,int base,int offset,
215     int target,int keep_ll_bit,
216     memop_fast_access op_handler)
217     {
218     m_uint32_t val = sign_extend(offset,16);
219 dpavlin 11 u_char *test1,*test2,*p_exit;
220 dpavlin 7
221     test2 = NULL;
222    
223     /* RSI = GPR[base] + sign-extended offset */
224     mips64_load_imm(b,AMD64_RSI,val);
225     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,
226     AMD64_RSI,AMD64_R15,REG_OFFSET(base));
227    
228     /* RBX = mts64_entry index */
229     amd64_mov_reg_reg_size(b->jit_ptr,X86_EBX,X86_ESI,4);
230     amd64_shift_reg_imm_size(b->jit_ptr,X86_SHR,X86_EBX,MTS64_HASH_SHIFT,4);
231     amd64_alu_reg_imm_size(b->jit_ptr,X86_AND,X86_EBX,MTS64_HASH_MASK,4);
232    
233     /* RCX = mts32 entry */
234     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,
235     AMD64_R15,
236     OFFSET(cpu_mips_t,mts_u.mts64_cache),8);
237     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RBX,5); /* TO FIX */
238     amd64_alu_reg_reg(b->jit_ptr,X86_ADD,AMD64_RCX,AMD64_RBX);
239    
240     /* Compare virtual page address (EAX = vpage) */
241     amd64_mov_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RSI,8);
242     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RAX,MIPS_MIN_PAGE_MASK);
243    
244     amd64_alu_reg_membase_size(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX,
245     OFFSET(mts64_entry_t,gvpa),8);
246     test1 = b->jit_ptr;
247     x86_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
248    
249     /* Test if we are writing to a COW page */
250     if (write_op) {
251     amd64_test_membase_imm_size(b->jit_ptr,
252     AMD64_RCX,OFFSET(mts64_entry_t,flags),
253     MTS_FLAG_COW,4);
254     test2 = b->jit_ptr;
255     amd64_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
256     }
257    
258     /* ESI = offset in page, RBX = Host Page Address */
259     amd64_alu_reg_imm(b->jit_ptr,X86_AND,X86_ESI,MIPS_MIN_PAGE_IMASK);
260     amd64_mov_reg_membase(b->jit_ptr,AMD64_RBX,
261     AMD64_RCX,OFFSET(mts64_entry_t,hpa),8);
262    
263     /* Memory access */
264     op_handler(b,target);
265    
266     p_exit = b->jit_ptr;
267     amd64_jump8(b->jit_ptr,0);
268     if (test2)
269     amd64_patch(test2,b->jit_ptr);
270    
271     /* === Slow lookup === */
272     amd64_patch(test1,b->jit_ptr);
273    
274     /* Save PC for exception handling */
275     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
276    
277     /* Sign-extend virtual address */
278     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RSI,X86_ESI);
279    
280     /* RDX = target register */
281     amd64_mov_reg_imm(b->jit_ptr,AMD64_RDX,target);
282    
283     /* RDI = CPU instance */
284     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
285    
286     /* Call memory access function */
287     amd64_call_membase(b->jit_ptr,AMD64_R15,MEMOP_OFFSET(opcode));
288    
289     amd64_patch(p_exit,b->jit_ptr);
290     }
291    
292     /* Fast memory operation (32-bit) */
293     static void mips64_emit_memop_fast32(mips64_jit_tcb_t *b,int write_op,
294     int opcode,int base,int offset,
295     int target,int keep_ll_bit,
296     memop_fast_access op_handler)
297     {
298     m_uint32_t val = sign_extend(offset,16);
299 dpavlin 11 u_char *test1,*test2,*p_exit;
300 dpavlin 7
301     test2 = NULL;
302    
303     /* ESI = GPR[base] + sign-extended offset */
304     amd64_mov_reg_imm(b->jit_ptr,X86_ESI,val);
305     amd64_alu_reg_membase_size(b->jit_ptr,X86_ADD,
306     X86_ESI,AMD64_R15,REG_OFFSET(base),4);
307    
308     /* RBX = mts32_entry index */
309     amd64_mov_reg_reg_size(b->jit_ptr,X86_EBX,X86_ESI,4);
310     amd64_shift_reg_imm_size(b->jit_ptr,X86_SHR,X86_EBX,MTS32_HASH_SHIFT,4);
311     amd64_alu_reg_imm_size(b->jit_ptr,X86_AND,X86_EBX,MTS32_HASH_MASK,4);
312    
313     /* RCX = mts32 entry */
314     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,
315     AMD64_R15,
316     OFFSET(cpu_mips_t,mts_u.mts32_cache),8);
317     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RBX,5); /* TO FIX */
318     amd64_alu_reg_reg(b->jit_ptr,X86_ADD,AMD64_RCX,AMD64_RBX);
319    
320     /* Compare virtual page address (EAX = vpage) */
321     amd64_mov_reg_reg(b->jit_ptr,X86_EAX,X86_ESI,4);
322     amd64_alu_reg_imm(b->jit_ptr,X86_AND,X86_EAX,MIPS_MIN_PAGE_MASK);
323    
324     amd64_alu_reg_membase_size(b->jit_ptr,X86_CMP,X86_EAX,AMD64_RCX,
325     OFFSET(mts32_entry_t,gvpa),4);
326     test1 = b->jit_ptr;
327     x86_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
328    
329     /* Test if we are writing to a COW page */
330     if (write_op) {
331     amd64_test_membase_imm_size(b->jit_ptr,
332     AMD64_RCX,OFFSET(mts32_entry_t,flags),
333     MTS_FLAG_COW,4);
334     test2 = b->jit_ptr;
335     amd64_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
336     }
337    
338     /* ESI = offset in page, RBX = Host Page Address */
339     amd64_alu_reg_imm(b->jit_ptr,X86_AND,X86_ESI,MIPS_MIN_PAGE_IMASK);
340     amd64_mov_reg_membase(b->jit_ptr,AMD64_RBX,
341     AMD64_RCX,OFFSET(mts32_entry_t,hpa),8);
342    
343     /* Memory access */
344     op_handler(b,target);
345    
346     p_exit = b->jit_ptr;
347     amd64_jump8(b->jit_ptr,0);
348    
349     /* === Slow lookup === */
350     amd64_patch(test1,b->jit_ptr);
351     if (test2)
352     amd64_patch(test2,b->jit_ptr);
353    
354     /* Save PC for exception handling */
355     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
356    
357     /* Sign-extend virtual address */
358     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RSI,X86_ESI);
359    
360     /* RDX = target register */
361     amd64_mov_reg_imm(b->jit_ptr,AMD64_RDX,target);
362    
363     /* RDI = CPU instance */
364     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
365    
366     /* Call memory access function */
367     amd64_call_membase(b->jit_ptr,AMD64_R15,MEMOP_OFFSET(opcode));
368    
369     amd64_patch(p_exit,b->jit_ptr);
370     }
371    
372     /* Fast memory operation */
373     static void mips64_emit_memop_fast(cpu_mips_t *cpu,mips64_jit_tcb_t *b,
374     int write_op,int opcode,
375     int base,int offset,
376     int target,int keep_ll_bit,
377     memop_fast_access op_handler)
378     {
379     switch(cpu->addr_mode) {
380     case 32:
381     mips64_emit_memop_fast32(b,write_op,opcode,base,offset,target,
382     keep_ll_bit,op_handler);
383     break;
384     case 64:
385     mips64_emit_memop_fast64(b,write_op,opcode,base,offset,target,
386     keep_ll_bit,op_handler);
387     break;
388     }
389     }
390    
391     /* Memory operation */
392     static void mips64_emit_memop(mips64_jit_tcb_t *b,int op,int base,int offset,
393     int target,int keep_ll_bit)
394     {
395     m_uint64_t val = sign_extend(offset,16);
396    
397     /* Save PC for exception handling */
398     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
399    
400     /* RDI = CPU instance */
401     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
402    
403     if (!keep_ll_bit) {
404     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
405     amd64_mov_membase_reg(b->jit_ptr,AMD64_RDI,OFFSET(cpu_mips_t,ll_bit),
406     X86_ECX,4);
407     }
408    
409     /* RSI = GPR[base] + sign-extended offset */
410     mips64_load_imm(b,AMD64_RSI,val);
411     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,
412     AMD64_RSI,AMD64_RDI,REG_OFFSET(base));
413    
414     /* RDX = target register */
415     amd64_mov_reg_imm(b->jit_ptr,AMD64_RDX,target);
416    
417     /* Call memory access function */
418     amd64_call_membase(b->jit_ptr,AMD64_RDI,MEMOP_OFFSET(op));
419     }
420    
421     /* Coprocessor Register transfert operation */
422     static void mips64_emit_cp_xfr_op(mips64_jit_tcb_t *b,int rt,int rd,void *f)
423     {
424     /* update pc */
425     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
426    
427     /* cp0 register */
428     amd64_mov_reg_imm(b->jit_ptr,AMD64_RDX,rd);
429    
430     /* gpr */
431     amd64_mov_reg_imm(b->jit_ptr,AMD64_RSI,rt);
432    
433     /* cpu instance */
434     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
435    
436     mips64_emit_basic_c_call(b,f);
437     }
438    
439     /* Virtual Breakpoint */
440     void mips64_emit_breakpoint(mips64_jit_tcb_t *b)
441     {
442     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
443     mips64_emit_c_call(b,mips64_run_breakpoint);
444     }
445    
446     /* Unknown opcode handler */
447     static fastcall void mips64_unknown_opcode(cpu_mips_t *cpu,m_uint32_t opcode)
448     {
449     printf("CPU = %p\n",cpu);
450    
451     printf("MIPS64: unhandled opcode 0x%8.8x at 0x%llx (ra=0x%llx)\n",
452     opcode,cpu->pc,cpu->gpr[MIPS_GPR_RA]);
453    
454     mips64_dump_regs(cpu->gen);
455     }
456    
457     /* Emit unhandled instruction code */
458     static int mips64_emit_unknown(cpu_mips_t *cpu,mips64_jit_tcb_t *b,
459     mips_insn_t opcode)
460     {
461     amd64_mov_reg_imm(b->jit_ptr,AMD64_RSI,opcode);
462     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
463    
464     mips64_emit_c_call(b,mips64_unknown_opcode);
465     return(0);
466     }
467    
468     /* Invalid delay slot handler */
469     static fastcall void mips64_invalid_delay_slot(cpu_mips_t *cpu)
470     {
471     printf("MIPS64: invalid instruction in delay slot at 0x%llx (ra=0x%llx)\n",
472     cpu->pc,cpu->gpr[MIPS_GPR_RA]);
473    
474     mips64_dump_regs(cpu->gen);
475    
476     /* Halt the virtual CPU */
477     cpu->pc = 0;
478     }
479    
480     /* Emit unhandled instruction code */
481     int mips64_emit_invalid_delay_slot(mips64_jit_tcb_t *b)
482     {
483     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
484     mips64_emit_c_call(b,mips64_invalid_delay_slot);
485     return(0);
486     }
487    
488     /*
489     * Increment count register and trigger the timer IRQ if value in compare
490     * register is the same.
491     */
492     void mips64_inc_cp0_count_reg(mips64_jit_tcb_t *b)
493     {
494     amd64_inc_membase(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,cp0_virt_cnt_reg));
495    
496     #if 0 /* TIMER_IRQ */
497     u_char *test1;
498    
499     /* increment the virtual count register */
500     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,
501     AMD64_R15,OFFSET(cpu_mips_t,cp0_virt_cnt_reg),4);
502     amd64_inc_reg_size(b->jit_ptr,AMD64_RAX,4);
503     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,
504     OFFSET(cpu_mips_t,cp0_virt_cnt_reg),
505     AMD64_RAX,4);
506    
507     /* check with the virtual compare register */
508     amd64_alu_reg_membase_size(b->jit_ptr,X86_CMP,AMD64_RAX,
509     AMD64_R15,OFFSET(cpu_mips_t,cp0_virt_cmp_reg),4);
510     test1 = b->jit_ptr;
511     amd64_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
512    
513     /* we have to trigger the timer irq */
514     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
515     mips64_emit_basic_c_call(b,mips64_trigger_timer_irq);
516    
517     amd64_patch(test1,b->jit_ptr);
518     #endif
519     }
520    
521     /* Check if there are pending IRQ */
522     void mips64_check_pending_irq(mips64_jit_tcb_t *b)
523     {
524     u_char *test1;
525    
526     /* Check the pending IRQ flag */
527     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,
528     AMD64_R15,OFFSET(cpu_mips_t,irq_pending),4);
529    
530     amd64_test_reg_reg_size(b->jit_ptr,AMD64_RAX,AMD64_RAX,4);
531     test1 = b->jit_ptr;
532     amd64_branch8(b->jit_ptr, X86_CC_Z, 0, 1);
533    
534     /* Update PC */
535     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
536    
537     /* Trigger the IRQ */
538     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
539     mips64_emit_basic_c_call(b,mips64_trigger_irq);
540     mips64_jit_tcb_push_epilog(b);
541    
542     amd64_patch(test1,b->jit_ptr);
543     }
544    
545     /* Increment the number of executed instructions (performance debugging) */
546     void mips64_inc_perf_counter(mips64_jit_tcb_t *b)
547     {
548 dpavlin 11 amd64_inc_membase_size(b->jit_ptr,
549     AMD64_R15,OFFSET(cpu_mips_t,perf_counter),4);
550 dpavlin 7 }
551    
552     /* ADD */
553     DECLARE_INSN(ADD)
554     {
555     int rs = bits(insn,21,25);
556     int rt = bits(insn,16,20);
557     int rd = bits(insn,11,15);
558    
559     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
560     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RAX,AMD64_R15,
561     REG_OFFSET(rt));
562    
563     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
564     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
565     return(0);
566     }
567    
568     /* ADDI */
569     DECLARE_INSN(ADDI)
570     {
571     int rs = bits(insn,21,25);
572     int rt = bits(insn,16,20);
573     int imm = bits(insn,0,15);
574     m_uint64_t val = sign_extend(imm,16);
575    
576     /* TODO: Exception handling */
577    
578     mips64_load_imm(b,AMD64_RAX,val);
579     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RAX,
580     AMD64_R15,REG_OFFSET(rs));
581    
582     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
583     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RAX,8);
584     return(0);
585     }
586    
587     /* ADDIU */
588     DECLARE_INSN(ADDIU)
589     {
590     int rs = bits(insn,21,25);
591     int rt = bits(insn,16,20);
592     int imm = bits(insn,0,15);
593     m_uint64_t val = sign_extend(imm,16);
594    
595     mips64_load_imm(b,AMD64_RAX,val);
596    
597     if (rs != 0) {
598     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RAX,
599     AMD64_R15,REG_OFFSET(rs));
600     }
601    
602     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EAX);
603     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RDX,8);
604     return(0);
605     }
606    
607     /* ADDU */
608     DECLARE_INSN(ADDU)
609     {
610     int rs = bits(insn,21,25);
611     int rt = bits(insn,16,20);
612     int rd = bits(insn,11,15);
613    
614     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
615     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RAX,AMD64_R15,
616     REG_OFFSET(rt));
617    
618     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
619     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
620     return(0);
621     }
622    
623     /* AND */
624     DECLARE_INSN(AND)
625     {
626     int rs = bits(insn,21,25);
627     int rt = bits(insn,16,20);
628     int rd = bits(insn,11,15);
629    
630     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
631     amd64_alu_reg_membase(b->jit_ptr,X86_AND,AMD64_RAX,AMD64_R15,
632     REG_OFFSET(rt));
633     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
634     return(0);
635     }
636    
637     /* ANDI */
638     DECLARE_INSN(ANDI)
639     {
640     int rs = bits(insn,21,25);
641     int rt = bits(insn,16,20);
642     int imm = bits(insn,0,15);
643    
644     mips64_load_imm(b,AMD64_RAX,imm);
645    
646     amd64_alu_reg_membase(b->jit_ptr,X86_AND,AMD64_RAX,
647     AMD64_R15,REG_OFFSET(rs));
648    
649     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RAX,8);
650     return(0);
651     }
652    
653     /* B (Branch, virtual instruction) */
654     DECLARE_INSN(B)
655     {
656     int offset = bits(insn,0,15);
657     m_uint64_t new_pc;
658    
659     /* compute the new pc */
660     new_pc = b->start_pc + (b->mips_trans_pos << 2);
661     new_pc += sign_extend(offset << 2,18);
662    
663     /* insert the instruction in the delay slot */
664     mips64_jit_fetch_and_emit(cpu,b,1);
665    
666     /* set the new pc in cpu structure */
667     mips64_set_jump(cpu,b,new_pc,1);
668     return(0);
669     }
670    
671     /* BAL (Branch and Link, virtual instruction) */
672     DECLARE_INSN(BAL)
673     {
674     int offset = bits(insn,0,15);
675     m_uint64_t new_pc;
676    
677     /* compute the new pc */
678     new_pc = b->start_pc + (b->mips_trans_pos << 2);
679     new_pc += sign_extend(offset << 2,18);
680    
681     /* set the return address (instruction after the delay slot) */
682     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
683    
684     /* insert the instruction in the delay slot */
685     mips64_jit_fetch_and_emit(cpu,b,1);
686    
687     /* set the new pc in cpu structure */
688     mips64_set_jump(cpu,b,new_pc,0);
689     return(0);
690     }
691    
692     /* BEQ (Branch On Equal) */
693     DECLARE_INSN(BEQ)
694     {
695     int rs = bits(insn,21,25);
696     int rt = bits(insn,16,20);
697     int offset = bits(insn,0,15);
698     u_char *test1;
699     m_uint64_t new_pc;
700    
701     /* compute the new pc */
702     new_pc = b->start_pc + (b->mips_trans_pos << 2);
703     new_pc += sign_extend(offset << 2,18);
704    
705     /*
706     * compare gpr[rs] and gpr[rt].
707     */
708     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
709     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
710     AMD64_R15,REG_OFFSET(rt));
711     test1 = b->jit_ptr;
712     amd64_branch32(b->jit_ptr, X86_CC_NE, 0, 1);
713    
714     /* insert the instruction in the delay slot */
715     mips64_jit_fetch_and_emit(cpu,b,2);
716    
717     /* set the new pc in cpu structure */
718     mips64_set_jump(cpu,b,new_pc,1);
719    
720     amd64_patch(test1,b->jit_ptr);
721    
722     /* if the branch is not taken, we have to execute the delay slot too */
723     mips64_jit_fetch_and_emit(cpu,b,1);
724     return(0);
725     }
726    
727     /* BEQL (Branch On Equal Likely) */
728     DECLARE_INSN(BEQL)
729     {
730     int rs = bits(insn,21,25);
731     int rt = bits(insn,16,20);
732     int offset = bits(insn,0,15);
733     u_char *test1;
734     m_uint64_t new_pc;
735    
736     /* compute the new pc */
737     new_pc = b->start_pc + (b->mips_trans_pos << 2);
738     new_pc += sign_extend(offset << 2,18);
739    
740     /*
741     * compare gpr[rs] and gpr[rt].
742     */
743     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
744     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
745     AMD64_R15,REG_OFFSET(rt));
746     test1 = b->jit_ptr;
747     amd64_branch32(b->jit_ptr, X86_CC_NE, 0, 1);
748    
749     /* insert the instruction in the delay slot */
750     mips64_jit_fetch_and_emit(cpu,b,1);
751    
752     /* set the new pc in cpu structure */
753     mips64_set_jump(cpu,b,new_pc,1);
754    
755     amd64_patch(test1,b->jit_ptr);
756     return(0);
757     }
758    
759     /* BEQZ (Branch On Equal Zero) */
760     DECLARE_INSN(BEQZ)
761     {
762     int rs = bits(insn,21,25);
763     int offset = bits(insn,0,15);
764     u_char *test1;
765     m_uint64_t new_pc;
766    
767     /* compute the new pc */
768     new_pc = b->start_pc + (b->mips_trans_pos << 2);
769     new_pc += sign_extend(offset << 2,18);
770    
771     /*
772     * compare gpr[rs] with 0.
773     */
774     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
775     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
776     test1 = b->jit_ptr;
777     amd64_branch32(b->jit_ptr, X86_CC_NZ, 0, 1);
778    
779     /* insert the instruction in the delay slot */
780     mips64_jit_fetch_and_emit(cpu,b,2);
781    
782     /* set the new pc in cpu structure */
783     mips64_set_jump(cpu,b,new_pc,1);
784    
785     amd64_patch(test1,b->jit_ptr);
786    
787     /* if the branch is not taken, we have to execute the delay slot too */
788     mips64_jit_fetch_and_emit(cpu,b,1);
789     return(0);
790     }
791    
792     /* BNEZ (Branch On Not Equal Zero) */
793     DECLARE_INSN(BNEZ)
794     {
795     int rs = bits(insn,21,25);
796     int offset = bits(insn,0,15);
797     u_char *test1;
798     m_uint64_t new_pc;
799    
800     /* compute the new pc */
801     new_pc = b->start_pc + (b->mips_trans_pos << 2);
802     new_pc += sign_extend(offset << 2,18);
803    
804     /*
805     * compare gpr[rs] with 0.
806     */
807     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
808     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
809     test1 = b->jit_ptr;
810     amd64_branch32(b->jit_ptr, X86_CC_Z, 0, 1);
811    
812     /* insert the instruction in the delay slot */
813     mips64_jit_fetch_and_emit(cpu,b,2);
814    
815     /* set the new pc in cpu structure */
816     mips64_set_jump(cpu,b,new_pc,1);
817    
818     amd64_patch(test1,b->jit_ptr);
819    
820     /* if the branch is not taken, we have to execute the delay slot too */
821     mips64_jit_fetch_and_emit(cpu,b,1);
822     return(0);
823     }
824    
825     /* BGEZ (Branch On Greater or Equal Than Zero) */
826     DECLARE_INSN(BGEZ)
827     {
828     int rs = bits(insn,21,25);
829     int offset = bits(insn,0,15);
830     u_char *test1;
831     m_uint64_t new_pc;
832    
833     /* compute the new pc */
834     new_pc = b->start_pc + (b->mips_trans_pos << 2);
835     new_pc += sign_extend(offset << 2,18);
836    
837     /* If sign bit is set, don't take the branch */
838     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
839     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
840     test1 = b->jit_ptr;
841     amd64_branch32(b->jit_ptr, X86_CC_S, 0, 1);
842    
843     /* insert the instruction in the delay slot */
844     mips64_jit_fetch_and_emit(cpu,b,2);
845    
846     /* set the new pc in cpu structure */
847     mips64_set_jump(cpu,b,new_pc,1);
848    
849     amd64_patch(test1,b->jit_ptr);
850    
851     /* if the branch is not taken, we have to execute the delay slot too */
852     mips64_jit_fetch_and_emit(cpu,b,1);
853     return(0);
854     }
855    
856     /* BGEZAL (Branch On Greater or Equal Than Zero And Link) */
857     DECLARE_INSN(BGEZAL)
858     {
859     int rs = bits(insn,21,25);
860     int offset = bits(insn,0,15);
861     u_char *test1;
862     m_uint64_t new_pc;
863    
864     /* compute the new pc */
865     new_pc = b->start_pc + (b->mips_trans_pos << 2);
866     new_pc += sign_extend(offset << 2,18);
867    
868     /* set the return address (instruction after the delay slot) */
869     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
870    
871     /* If sign bit is set, don't take the branch */
872     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
873     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
874     test1 = b->jit_ptr;
875     amd64_branch32(b->jit_ptr, X86_CC_S, 0, 1);
876    
877     /* insert the instruction in the delay slot */
878     mips64_jit_fetch_and_emit(cpu,b,2);
879    
880     /* set the new pc in cpu structure */
881     mips64_set_jump(cpu,b,new_pc,1);
882    
883     amd64_patch(test1,b->jit_ptr);
884    
885     /* if the branch is not taken, we have to execute the delay slot too */
886     mips64_jit_fetch_and_emit(cpu,b,1);
887     return(0);
888     }
889    
890     /* BGEZALL (Branch On Greater or Equal Than Zero And Link Likely) */
891     DECLARE_INSN(BGEZALL)
892     {
893     int rs = bits(insn,21,25);
894     int offset = bits(insn,0,15);
895     u_char *test1;
896     m_uint64_t new_pc;
897    
898     /* compute the new pc */
899     new_pc = b->start_pc + (b->mips_trans_pos << 2);
900     new_pc += sign_extend(offset << 2,18);
901    
902     /* set the return address (instruction after the delay slot) */
903     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
904    
905     /* If sign bit is set, don't take the branch */
906     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
907     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
908     test1 = b->jit_ptr;
909     amd64_branch32(b->jit_ptr, X86_CC_S, 0, 1);
910    
911     /* insert the instruction in the delay slot */
912     mips64_jit_fetch_and_emit(cpu,b,1);
913    
914     /* set the new pc in cpu structure */
915     mips64_set_jump(cpu,b,new_pc,1);
916    
917     amd64_patch(test1,b->jit_ptr);
918     return(0);
919     }
920    
921     /* BGEZL (Branch On Greater or Equal Than Zero Likely) */
922     DECLARE_INSN(BGEZL)
923     {
924     int rs = bits(insn,21,25);
925     int offset = bits(insn,0,15);
926     u_char *test1;
927     m_uint64_t new_pc;
928    
929     /* compute the new pc */
930     new_pc = b->start_pc + (b->mips_trans_pos << 2);
931     new_pc += sign_extend(offset << 2,18);
932    
933     /* If sign bit is set, don't take the branch */
934     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
935     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
936     test1 = b->jit_ptr;
937     amd64_branch32(b->jit_ptr, X86_CC_S, 0, 1);
938    
939     /* insert the instruction in the delay slot */
940     mips64_jit_fetch_and_emit(cpu,b,1);
941    
942     /* set the new pc in cpu structure */
943     mips64_set_jump(cpu,b,new_pc,1);
944    
945     amd64_patch(test1,b->jit_ptr);
946     return(0);
947     }
948    
949     /* BGTZ (Branch On Greater Than Zero) */
950     DECLARE_INSN(BGTZ)
951     {
952     int rs = bits(insn,21,25);
953     int offset = bits(insn,0,15);
954     u_char *test1;
955     m_uint64_t new_pc;
956    
957     /* compute the new pc */
958     new_pc = b->start_pc + (b->mips_trans_pos << 2);
959     new_pc += sign_extend(offset << 2,18);
960    
961     /* compare reg to zero */
962     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
963     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
964    
965     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX);
966     test1 = b->jit_ptr;
967     amd64_branch32(b->jit_ptr, X86_CC_LE, 0, 1);
968    
969     /* insert the instruction in the delay slot */
970     mips64_jit_fetch_and_emit(cpu,b,2);
971    
972     /* set the new pc in cpu structure */
973     mips64_set_jump(cpu,b,new_pc,1);
974    
975     amd64_patch(test1,b->jit_ptr);
976    
977     /* if the branch is not taken, we have to execute the delay slot too */
978     mips64_jit_fetch_and_emit(cpu,b,1);
979     return(0);
980     }
981    
982     /* BGTZL (Branch On Greater Than Zero Likely) */
983     DECLARE_INSN(BGTZL)
984     {
985     int rs = bits(insn,21,25);
986     int offset = bits(insn,0,15);
987     u_char *test1;
988     m_uint64_t new_pc;
989    
990     /* compute the new pc */
991     new_pc = b->start_pc + (b->mips_trans_pos << 2);
992     new_pc += sign_extend(offset << 2,18);
993    
994     /* compare reg to zero */
995     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
996     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
997    
998     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX);
999     test1 = b->jit_ptr;
1000     amd64_branch32(b->jit_ptr, X86_CC_LE, 0, 1);
1001    
1002     /* insert the instruction in the delay slot */
1003     mips64_jit_fetch_and_emit(cpu,b,1);
1004    
1005     /* set the new pc in cpu structure */
1006     mips64_set_jump(cpu,b,new_pc,1);
1007    
1008     amd64_patch(test1,b->jit_ptr);
1009     return(0);
1010     }
1011    
1012     /* BLEZ (Branch On Less or Equal Than Zero) */
1013     DECLARE_INSN(BLEZ)
1014     {
1015     int rs = bits(insn,21,25);
1016     int offset = bits(insn,0,15);
1017     u_char *test1;
1018     m_uint64_t new_pc;
1019    
1020     /* compute the new pc */
1021     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1022     new_pc += sign_extend(offset << 2,18);
1023    
1024     /* compare reg to zero */
1025     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1026     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
1027    
1028     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX);
1029     test1 = b->jit_ptr;
1030     amd64_branch32(b->jit_ptr, X86_CC_GT, 0, 1);
1031    
1032     /* insert the instruction in the delay slot */
1033     mips64_jit_fetch_and_emit(cpu,b,2);
1034    
1035     /* set the new pc in cpu structure */
1036     mips64_set_jump(cpu,b,new_pc,1);
1037    
1038     amd64_patch(test1,b->jit_ptr);
1039    
1040     /* if the branch is not taken, we have to execute the delay slot too */
1041     mips64_jit_fetch_and_emit(cpu,b,1);
1042     return(0);
1043     }
1044    
1045     /* BLEZL (Branch On Less or Equal Than Zero Likely) */
1046     DECLARE_INSN(BLEZL)
1047     {
1048     int rs = bits(insn,21,25);
1049     int offset = bits(insn,0,15);
1050     u_char *test1;
1051     m_uint64_t new_pc;
1052    
1053     /* compute the new pc */
1054     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1055     new_pc += sign_extend(offset << 2,18);
1056    
1057     /* compare reg to zero */
1058     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1059     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
1060    
1061     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RCX);
1062     test1 = b->jit_ptr;
1063     amd64_branch32(b->jit_ptr, X86_CC_GT, 0, 1);
1064    
1065     /* insert the instruction in the delay slot */
1066     mips64_jit_fetch_and_emit(cpu,b,1);
1067    
1068     /* set the new pc in cpu structure */
1069     mips64_set_jump(cpu,b,new_pc,1);
1070    
1071     amd64_patch(test1,b->jit_ptr);
1072     return(0);
1073     }
1074    
1075     /* BLTZ (Branch On Less Than Zero) */
1076     DECLARE_INSN(BLTZ)
1077     {
1078     int rs = bits(insn,21,25);
1079     int offset = bits(insn,0,15);
1080     u_char *test1;
1081     m_uint64_t new_pc;
1082    
1083     /* compute the new pc */
1084     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1085     new_pc += sign_extend(offset << 2,18);
1086    
1087     /* If sign bit isn't set, don't take the branch */
1088     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1089     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
1090     test1 = b->jit_ptr;
1091     amd64_branch32(b->jit_ptr, X86_CC_NS, 0, 1);
1092    
1093     /* insert the instruction in the delay slot */
1094     mips64_jit_fetch_and_emit(cpu,b,2);
1095    
1096     /* set the new pc in cpu structure */
1097     mips64_set_jump(cpu,b,new_pc,1);
1098    
1099     amd64_patch(test1,b->jit_ptr);
1100    
1101     /* if the branch is not taken, we have to execute the delay slot too */
1102     mips64_jit_fetch_and_emit(cpu,b,1);
1103     return(0);
1104     }
1105    
1106     /* BLTZAL (Branch On Less Than Zero And Link) */
1107     DECLARE_INSN(BLTZAL)
1108     {
1109     int rs = bits(insn,21,25);
1110     int offset = bits(insn,0,15);
1111     u_char *test1;
1112     m_uint64_t new_pc;
1113    
1114     /* compute the new pc */
1115     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1116     new_pc += sign_extend(offset << 2,18);
1117    
1118     /* set the return address (instruction after the delay slot) */
1119     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
1120    
1121     /* If sign bit isn't set, don't take the branch */
1122     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1123     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
1124     test1 = b->jit_ptr;
1125     amd64_branch32(b->jit_ptr, X86_CC_NS, 0, 1);
1126    
1127     /* insert the instruction in the delay slot */
1128     mips64_jit_fetch_and_emit(cpu,b,2);
1129    
1130     /* set the new pc in cpu structure */
1131     mips64_set_jump(cpu,b,new_pc,1);
1132    
1133     amd64_patch(test1,b->jit_ptr);
1134    
1135     /* if the branch is not taken, we have to execute the delay slot too */
1136     mips64_jit_fetch_and_emit(cpu,b,1);
1137     return(0);
1138     }
1139    
1140     /* BLTZALL (Branch On Less Than Zero And Link Likely) */
1141     DECLARE_INSN(BLTZALL)
1142     {
1143     int rs = bits(insn,21,25);
1144     int offset = bits(insn,0,15);
1145     u_char *test1;
1146     m_uint64_t new_pc;
1147    
1148     /* compute the new pc */
1149     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1150     new_pc += sign_extend(offset << 2,18);
1151    
1152     /* set the return address (instruction after the delay slot) */
1153     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
1154    
1155     /* If sign bit isn't set, don't take the branch */
1156     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1157     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
1158     test1 = b->jit_ptr;
1159     amd64_branch32(b->jit_ptr, X86_CC_NS, 0, 1);
1160    
1161     /* insert the instruction in the delay slot */
1162     mips64_jit_fetch_and_emit(cpu,b,1);
1163    
1164     /* set the new pc in cpu structure */
1165     mips64_set_jump(cpu,b,new_pc,1);
1166    
1167     amd64_patch(test1,b->jit_ptr);
1168     return(0);
1169     }
1170    
1171     /* BLTZL (Branch On Less Than Zero Likely) */
1172     DECLARE_INSN(BLTZL)
1173     {
1174     int rs = bits(insn,21,25);
1175     int offset = bits(insn,0,15);
1176     u_char *test1;
1177     m_uint64_t new_pc;
1178    
1179     /* compute the new pc */
1180     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1181     new_pc += sign_extend(offset << 2,18);
1182    
1183     /* If sign bit isn't set, don't take the branch */
1184     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1185     amd64_test_reg_reg(b->jit_ptr,AMD64_RAX,AMD64_RAX);
1186     test1 = b->jit_ptr;
1187     amd64_branch32(b->jit_ptr, X86_CC_NS, 0, 1);
1188    
1189     /* insert the instruction in the delay slot */
1190     mips64_jit_fetch_and_emit(cpu,b,1);
1191    
1192     /* set the new pc in cpu structure */
1193     mips64_set_jump(cpu,b,new_pc,1);
1194    
1195     amd64_patch(test1,b->jit_ptr);
1196     return(0);
1197     }
1198    
1199     /* BNE (Branch On Not Equal) */
1200     DECLARE_INSN(BNE)
1201     {
1202     int rs = bits(insn,21,25);
1203     int rt = bits(insn,16,20);
1204     int offset = bits(insn,0,15);
1205     u_char *test1;
1206     m_uint64_t new_pc;
1207    
1208     /* compute the new pc */
1209     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1210     new_pc += sign_extend(offset << 2,18);
1211    
1212     /*
1213     * compare gpr[rs] and gpr[rt].
1214     */
1215     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1216     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
1217     AMD64_R15,REG_OFFSET(rt));
1218     test1 = b->jit_ptr;
1219     amd64_branch32(b->jit_ptr, X86_CC_E, 0, 1);
1220    
1221     /* insert the instruction in the delay slot */
1222     mips64_jit_fetch_and_emit(cpu,b,2);
1223    
1224     /* set the new pc in cpu structure */
1225     mips64_set_jump(cpu,b,new_pc,1);
1226    
1227     amd64_patch(test1,b->jit_ptr);
1228    
1229     /* if the branch is not taken, we have to execute the delay slot too */
1230     mips64_jit_fetch_and_emit(cpu,b,1);
1231     return(0);
1232     }
1233    
1234     /* BNEL (Branch On Not Equal Likely) */
1235     DECLARE_INSN(BNEL)
1236     {
1237     int rs = bits(insn,21,25);
1238     int rt = bits(insn,16,20);
1239     int offset = bits(insn,0,15);
1240     u_char *test1;
1241     m_uint64_t new_pc;
1242    
1243     /* compute the new pc */
1244     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1245     new_pc += sign_extend(offset << 2,18);
1246    
1247     /*
1248     * compare gpr[rs] and gpr[rt].
1249     */
1250     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1251     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
1252     AMD64_R15,REG_OFFSET(rt));
1253     test1 = b->jit_ptr;
1254     amd64_branch32(b->jit_ptr, X86_CC_E, 0, 1);
1255    
1256     /* insert the instruction in the delay slot */
1257     mips64_jit_fetch_and_emit(cpu,b,1);
1258    
1259     /* set the new pc in cpu structure */
1260     mips64_set_jump(cpu,b,new_pc,1);
1261    
1262     amd64_patch(test1,b->jit_ptr);
1263     return(0);
1264     }
1265    
1266     /* BREAK */
1267     DECLARE_INSN(BREAK)
1268     {
1269     u_int code = bits(insn,6,25);
1270    
1271     amd64_mov_reg_imm(b->jit_ptr,AMD64_RSI,code);
1272     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
1273     mips64_emit_basic_c_call(b,mips64_exec_break);
1274     mips64_jit_tcb_push_epilog(b);
1275     return(0);
1276     }
1277    
1278     /* CACHE */
1279     DECLARE_INSN(CACHE)
1280     {
1281     int base = bits(insn,21,25);
1282     int op = bits(insn,16,20);
1283     int offset = bits(insn,0,15);
1284    
1285     mips64_emit_memop(b,MIPS_MEMOP_CACHE,base,offset,op,0);
1286     return(0);
1287     }
1288    
1289     /* CFC0 */
1290     DECLARE_INSN(CFC0)
1291     {
1292     int rt = bits(insn,16,20);
1293     int rd = bits(insn,11,15);
1294    
1295     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_cfc0);
1296     return(0);
1297     }
1298    
1299     /* CTC0 */
1300     DECLARE_INSN(CTC0)
1301     {
1302     int rt = bits(insn,16,20);
1303     int rd = bits(insn,11,15);
1304    
1305     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_ctc0);
1306     return(0);
1307     }
1308    
1309     /* DADDIU */
1310     DECLARE_INSN(DADDIU)
1311     {
1312     int rs = bits(insn,21,25);
1313     int rt = bits(insn,16,20);
1314     int imm = bits(insn,0,15);
1315     m_uint64_t val = sign_extend(imm,16);
1316    
1317     mips64_load_imm(b,AMD64_RCX,val);
1318     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RCX,
1319     AMD64_R15,REG_OFFSET(rs));
1320     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
1321     return(0);
1322     }
1323    
1324     /* DADDU: rd = rs + rt */
1325     DECLARE_INSN(DADDU)
1326     {
1327     int rs = bits(insn,21,25);
1328     int rt = bits(insn,16,20);
1329     int rd = bits(insn,11,15);
1330    
1331     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),8);
1332     amd64_alu_reg_membase(b->jit_ptr,X86_ADD,AMD64_RCX,
1333     AMD64_R15,REG_OFFSET(rt));
1334     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RCX,8);
1335     return(0);
1336     }
1337    
1338     /* DIV */
1339     DECLARE_INSN(DIV)
1340     {
1341     int rs = bits(insn,21,25);
1342     int rt = bits(insn,16,20);
1343    
1344     /* eax = gpr[rs] */
1345     amd64_clear_reg(b->jit_ptr,AMD64_RDX);
1346     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
1347    
1348     /* ecx = gpr[rt] */
1349     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
1350    
1351     /* eax = quotient (LO), edx = remainder (HI) */
1352     amd64_div_reg_size(b->jit_ptr,AMD64_RCX,1,4);
1353    
1354     /* store LO */
1355     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
1356     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,lo),
1357     AMD64_RAX,8);
1358    
1359     /* store HI */
1360     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
1361     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,hi),
1362     AMD64_RDX,8);
1363     return(0);
1364     }
1365    
1366     /* DIVU */
1367     DECLARE_INSN(DIVU)
1368     {
1369     int rs = bits(insn,21,25);
1370     int rt = bits(insn,16,20);
1371    
1372     /* eax = gpr[rs] */
1373     amd64_clear_reg(b->jit_ptr,AMD64_RDX);
1374     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
1375    
1376     /* ecx = gpr[rt] */
1377     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
1378    
1379     /* eax = quotient (LO), edx = remainder (HI) */
1380     amd64_div_reg_size(b->jit_ptr,AMD64_RCX,0,4);
1381    
1382     /* store LO */
1383     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
1384     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,lo),
1385     AMD64_RAX,8);
1386    
1387     /* store HI */
1388     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
1389     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,hi),
1390     AMD64_RDX,8);
1391     return(0);
1392     }
1393    
1394     /* DMFC0 */
1395     DECLARE_INSN(DMFC0)
1396     {
1397     int rt = bits(insn,16,20);
1398     int rd = bits(insn,11,15);
1399    
1400     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_dmfc0);
1401     return(0);
1402     }
1403    
1404     /* DMFC1 */
1405     DECLARE_INSN(DMFC1)
1406     {
1407     int rt = bits(insn,16,20);
1408     int rd = bits(insn,11,15);
1409    
1410     mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_dmfc1);
1411     return(0);
1412     }
1413    
1414     /* DMTC0 */
1415     DECLARE_INSN(DMTC0)
1416     {
1417     int rt = bits(insn,16,20);
1418     int rd = bits(insn,11,15);
1419    
1420     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_dmtc0);
1421     return(0);
1422     }
1423    
1424     /* DMTC1 */
1425     DECLARE_INSN(DMTC1)
1426     {
1427     int rt = bits(insn,16,20);
1428     int rd = bits(insn,11,15);
1429    
1430     mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_dmtc1);
1431     return(0);
1432     }
1433    
1434     /* DSLL */
1435     DECLARE_INSN(DSLL)
1436     {
1437     int rt = bits(insn,16,20);
1438     int rd = bits(insn,11,15);
1439     int sa = bits(insn,6,10);
1440    
1441     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1442     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RAX,sa);
1443     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1444     return(0);
1445     }
1446    
1447     /* DSLL32 */
1448     DECLARE_INSN(DSLL32)
1449     {
1450     int rt = bits(insn,16,20);
1451     int rd = bits(insn,11,15);
1452     int sa = bits(insn,6,10);
1453    
1454     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1455     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RAX,sa+32);
1456     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1457     return(0);
1458     }
1459    
1460     /* DSLLV */
1461     DECLARE_INSN(DSLLV)
1462     {
1463     int rs = bits(insn,21,25);
1464     int rt = bits(insn,16,20);
1465     int rd = bits(insn,11,15);
1466    
1467     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
1468     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x3f);
1469    
1470     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1471     amd64_shift_reg(b->jit_ptr,X86_SHL,AMD64_RAX);
1472     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1473     return(0);
1474     }
1475    
1476     /* DSRA */
1477     DECLARE_INSN(DSRA)
1478     {
1479     int rt = bits(insn,16,20);
1480     int rd = bits(insn,11,15);
1481     int sa = bits(insn,6,10);
1482    
1483     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1484     amd64_shift_reg_imm(b->jit_ptr,X86_SAR,AMD64_RAX,sa);
1485     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1486     return(0);
1487     }
1488    
1489     /* DSRA32 */
1490     DECLARE_INSN(DSRA32)
1491     {
1492     int rt = bits(insn,16,20);
1493     int rd = bits(insn,11,15);
1494     int sa = bits(insn,6,10);
1495    
1496     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1497     amd64_shift_reg_imm(b->jit_ptr,X86_SAR,AMD64_RAX,sa+32);
1498     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1499     return(0);
1500     }
1501    
1502     /* DSRAV */
1503     DECLARE_INSN(DSRAV)
1504     {
1505     int rs = bits(insn,21,25);
1506     int rt = bits(insn,16,20);
1507     int rd = bits(insn,11,15);
1508    
1509     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
1510     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x3f);
1511    
1512     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1513     amd64_shift_reg(b->jit_ptr,X86_SAR,AMD64_RAX);
1514     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1515     return(0);
1516     }
1517    
1518     /* DSRL */
1519     DECLARE_INSN(DSRL)
1520     {
1521     int rt = bits(insn,16,20);
1522     int rd = bits(insn,11,15);
1523     int sa = bits(insn,6,10);
1524    
1525     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1526     amd64_shift_reg_imm(b->jit_ptr,X86_SHR,AMD64_RAX,sa);
1527     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1528     return(0);
1529     }
1530    
1531     /* DSRL32 */
1532     DECLARE_INSN(DSRL32)
1533     {
1534     int rt = bits(insn,16,20);
1535     int rd = bits(insn,11,15);
1536     int sa = bits(insn,6,10);
1537    
1538     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1539     amd64_shift_reg_imm(b->jit_ptr,X86_SHR,AMD64_RAX,sa+32);
1540     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1541     return(0);
1542     }
1543    
1544     /* DSRLV */
1545     DECLARE_INSN(DSRLV)
1546     {
1547     int rs = bits(insn,21,25);
1548     int rt = bits(insn,16,20);
1549     int rd = bits(insn,11,15);
1550    
1551     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
1552     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x3f);
1553    
1554     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
1555     amd64_shift_reg(b->jit_ptr,X86_SHR,AMD64_RAX);
1556     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1557     return(0);
1558     }
1559    
1560     /* DSUBU: rd = rs - rt */
1561     DECLARE_INSN(DSUBU)
1562     {
1563     int rs = bits(insn,21,25);
1564     int rt = bits(insn,16,20);
1565     int rd = bits(insn,11,15);
1566    
1567     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
1568     amd64_alu_reg_membase(b->jit_ptr,X86_SUB,AMD64_RAX,
1569     AMD64_R15,REG_OFFSET(rt));
1570     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1571     return(0);
1572     }
1573    
1574     /* ERET */
1575     DECLARE_INSN(ERET)
1576     {
1577     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
1578     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
1579     mips64_emit_basic_c_call(b,mips64_exec_eret);
1580     mips64_jit_tcb_push_epilog(b);
1581     return(0);
1582     }
1583    
1584     /* J (Jump) */
1585     DECLARE_INSN(J)
1586     {
1587     u_int instr_index = bits(insn,0,25);
1588     m_uint64_t new_pc;
1589    
1590     /* compute the new pc */
1591     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1592     new_pc &= ~((1 << 28) - 1);
1593     new_pc |= instr_index << 2;
1594    
1595     /* insert the instruction in the delay slot */
1596     mips64_jit_fetch_and_emit(cpu,b,1);
1597    
1598     /* set the new pc in cpu structure */
1599     mips64_set_jump(cpu,b,new_pc,1);
1600     return(0);
1601     }
1602    
1603     /* JAL (Jump And Link) */
1604     DECLARE_INSN(JAL)
1605     {
1606     u_int instr_index = bits(insn,0,25);
1607     m_uint64_t new_pc;
1608    
1609     /* compute the new pc */
1610     new_pc = b->start_pc + (b->mips_trans_pos << 2);
1611     new_pc &= ~((1 << 28) - 1);
1612     new_pc |= instr_index << 2;
1613    
1614     /* set the return address (instruction after the delay slot) */
1615     mips64_set_ra(b,b->start_pc + ((b->mips_trans_pos + 1) << 2));
1616    
1617     /* insert the instruction in the delay slot */
1618     mips64_jit_fetch_and_emit(cpu,b,1);
1619    
1620     /* set the new pc in cpu structure */
1621     mips64_set_jump(cpu,b,new_pc,0);
1622     return(0);
1623     }
1624    
1625     /* JALR (Jump and Link Register) */
1626     DECLARE_INSN(JALR)
1627     {
1628     int rs = bits(insn,21,25);
1629     int rd = bits(insn,11,15);
1630     m_uint64_t ret_pc;
1631    
1632     /* set the return pc (instruction after the delay slot) in GPR[rd] */
1633     ret_pc = b->start_pc + ((b->mips_trans_pos + 1) << 2);
1634     mips64_load_imm(b,AMD64_RAX,ret_pc);
1635     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1636    
1637     /* get the new pc */
1638     amd64_mov_reg_membase(b->jit_ptr,AMD64_R14,AMD64_R15,REG_OFFSET(rs),8);
1639    
1640     #if DEBUG_JR0
1641     {
1642     u_char *test1;
1643    
1644     amd64_test_reg_reg(b->jit_ptr,AMD64_R14,AMD64_R14);
1645     test1 = b->jit_ptr;
1646     amd64_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
1647     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
1648     mips64_emit_c_call(b,mips64_debug_jr0);
1649     amd64_patch(test1,b->jit_ptr);
1650     }
1651     #endif
1652    
1653     /* insert the instruction in the delay slot */
1654     mips64_jit_fetch_and_emit(cpu,b,1);
1655    
1656     /* set the new pc */
1657     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,pc),
1658     AMD64_R14,8);
1659    
1660     /* returns to the caller which will determine the next path */
1661     mips64_jit_tcb_push_epilog(b);
1662     return(0);
1663     }
1664    
1665     /* JR (Jump Register) */
1666     DECLARE_INSN(JR)
1667     {
1668     int rs = bits(insn,21,25);
1669    
1670     /* get the new pc */
1671     amd64_mov_reg_membase(b->jit_ptr,AMD64_R14,AMD64_R15,REG_OFFSET(rs),8);
1672    
1673     #if DEBUG_JR0
1674     {
1675     u_char *test1;
1676    
1677     amd64_test_reg_reg(b->jit_ptr,AMD64_RCX,AMD64_RCX);
1678     test1 = b->jit_ptr;
1679     amd64_branch8(b->jit_ptr, X86_CC_NZ, 0, 1);
1680     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
1681     mips64_emit_c_call(b,mips64_debug_jr0);
1682     amd64_patch(test1,b->jit_ptr);
1683     }
1684     #endif
1685    
1686     /* insert the instruction in the delay slot */
1687     mips64_jit_fetch_and_emit(cpu,b,1);
1688    
1689     /* set the new pc */
1690     amd64_mov_membase_reg(b->jit_ptr,
1691     AMD64_R15,OFFSET(cpu_mips_t,pc),
1692     AMD64_R14,8);
1693    
1694     /* returns to the caller which will determine the next path */
1695     mips64_jit_tcb_push_epilog(b);
1696     return(0);
1697     }
1698    
1699     /* LB (Load Byte) */
1700     DECLARE_INSN(LB)
1701     {
1702     int base = bits(insn,21,25);
1703     int rt = bits(insn,16,20);
1704     int offset = bits(insn,0,15);
1705    
1706     mips64_emit_memop(b,MIPS_MEMOP_LB,base,offset,rt,TRUE);
1707     return(0);
1708     }
1709    
1710     /* LBU (Load Byte Unsigned) */
1711     DECLARE_INSN(LBU)
1712     {
1713     int base = bits(insn,21,25);
1714     int rt = bits(insn,16,20);
1715     int offset = bits(insn,0,15);
1716    
1717     mips64_emit_memop(b,MIPS_MEMOP_LBU,base,offset,rt,TRUE);
1718     return(0);
1719     }
1720    
1721     /* LD (Load Double-Word) */
1722     DECLARE_INSN(LD)
1723     {
1724     int base = bits(insn,21,25);
1725     int rt = bits(insn,16,20);
1726     int offset = bits(insn,0,15);
1727    
1728     mips64_emit_memop(b,MIPS_MEMOP_LD,base,offset,rt,TRUE);
1729     return(0);
1730     }
1731    
1732     /* LDC1 (Load Double-Word to Coprocessor 1) */
1733     DECLARE_INSN(LDC1)
1734     {
1735     int base = bits(insn,21,25);
1736     int ft = bits(insn,16,20);
1737     int offset = bits(insn,0,15);
1738    
1739     mips64_emit_memop(b,MIPS_MEMOP_LDC1,base,offset,ft,TRUE);
1740     return(0);
1741     }
1742    
1743     /* LDL (Load Double-Word Left) */
1744     DECLARE_INSN(LDL)
1745     {
1746     int base = bits(insn,21,25);
1747     int rt = bits(insn,16,20);
1748     int offset = bits(insn,0,15);
1749    
1750     mips64_emit_memop(b,MIPS_MEMOP_LDL,base,offset,rt,TRUE);
1751     return(0);
1752     }
1753    
1754     /* LDR (Load Double-Word Right) */
1755     DECLARE_INSN(LDR)
1756     {
1757     int base = bits(insn,21,25);
1758     int rt = bits(insn,16,20);
1759     int offset = bits(insn,0,15);
1760    
1761     mips64_emit_memop(b,MIPS_MEMOP_LDR,base,offset,rt,TRUE);
1762     return(0);
1763     }
1764    
1765     /* LH (Load Half-Word) */
1766     DECLARE_INSN(LH)
1767     {
1768     int base = bits(insn,21,25);
1769     int rt = bits(insn,16,20);
1770     int offset = bits(insn,0,15);
1771    
1772     mips64_emit_memop(b,MIPS_MEMOP_LH,base,offset,rt,TRUE);
1773     return(0);
1774     }
1775    
1776     /* LHU (Load Half-Word Unsigned) */
1777     DECLARE_INSN(LHU)
1778     {
1779     int base = bits(insn,21,25);
1780     int rt = bits(insn,16,20);
1781     int offset = bits(insn,0,15);
1782    
1783     mips64_emit_memop(b,MIPS_MEMOP_LHU,base,offset,rt,TRUE);
1784     return(0);
1785     }
1786    
1787     /* LI (virtual) */
1788     DECLARE_INSN(LI)
1789     {
1790     int rt = bits(insn,16,20);
1791     int imm = bits(insn,0,15);
1792     m_uint64_t val = sign_extend(imm,16);
1793    
1794     mips64_load_imm(b,AMD64_RCX,val);
1795     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
1796     return(0);
1797     }
1798    
1799     /* LL (Load Linked) */
1800     DECLARE_INSN(LL)
1801     {
1802     int base = bits(insn,21,25);
1803     int rt = bits(insn,16,20);
1804     int offset = bits(insn,0,15);
1805    
1806     mips64_emit_memop(b,MIPS_MEMOP_LL,base,offset,rt,TRUE);
1807     return(0);
1808     }
1809    
1810     /* LUI */
1811     DECLARE_INSN(LUI)
1812     {
1813     int rt = bits(insn,16,20);
1814     int imm = bits(insn,0,15);
1815     m_uint64_t val = sign_extend(imm,16) << 16;
1816    
1817     #if 1
1818     mips64_load_imm(b,AMD64_RCX,val);
1819     #else
1820     amd64_mov_reg_imm(b->jit_ptr,AMD64_RCX,imm);
1821     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RCX,48);
1822     amd64_shift_reg_imm(b->jit_ptr,X86_SAR,AMD64_RCX,32);
1823     #endif
1824    
1825     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
1826     return(0);
1827     }
1828    
1829     /* LW (Load Word) */
1830     DECLARE_INSN(LW)
1831     {
1832     int base = bits(insn,21,25);
1833     int rt = bits(insn,16,20);
1834     int offset = bits(insn,0,15);
1835    
1836     if (cpu->fast_memop) {
1837     mips64_emit_memop_fast(cpu,b,0,MIPS_MEMOP_LW,base,offset,rt,TRUE,
1838     mips64_memop_fast_lw);
1839     } else {
1840     mips64_emit_memop(b,MIPS_MEMOP_LW,base,offset,rt,TRUE);
1841     }
1842     return(0);
1843     }
1844    
1845     /* LWL (Load Word Left) */
1846     DECLARE_INSN(LWL)
1847     {
1848     int base = bits(insn,21,25);
1849     int rt = bits(insn,16,20);
1850     int offset = bits(insn,0,15);
1851    
1852     mips64_emit_memop(b,MIPS_MEMOP_LWL,base,offset,rt,TRUE);
1853     return(0);
1854     }
1855    
1856     /* LWR (Load Word Right) */
1857     DECLARE_INSN(LWR)
1858     {
1859     int base = bits(insn,21,25);
1860     int rt = bits(insn,16,20);
1861     int offset = bits(insn,0,15);
1862    
1863     mips64_emit_memop(b,MIPS_MEMOP_LWR,base,offset,rt,TRUE);
1864     return(0);
1865     }
1866    
1867     /* LWU (Load Word Unsigned) */
1868     DECLARE_INSN(LWU)
1869     {
1870     int base = bits(insn,21,25);
1871     int rt = bits(insn,16,20);
1872     int offset = bits(insn,0,15);
1873    
1874     mips64_emit_memop(b,MIPS_MEMOP_LWU,base,offset,rt,TRUE);
1875     return(0);
1876     }
1877    
1878     /* MFC0 */
1879     DECLARE_INSN(MFC0)
1880     {
1881     int rt = bits(insn,16,20);
1882     int rd = bits(insn,11,15);
1883    
1884     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_mfc0);
1885     return(0);
1886     }
1887    
1888     /* MFC1 */
1889     DECLARE_INSN(MFC1)
1890     {
1891     int rt = bits(insn,16,20);
1892     int rd = bits(insn,11,15);
1893    
1894     mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_mfc1);
1895     return(0);
1896     }
1897    
1898     /* MFHI */
1899     DECLARE_INSN(MFHI)
1900     {
1901     int rd = bits(insn,11,15);
1902    
1903     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,
1904     AMD64_R15,OFFSET(cpu_mips_t,hi),8);
1905     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RDX,8);
1906     return(0);
1907     }
1908    
1909     /* MFLO */
1910     DECLARE_INSN(MFLO)
1911     {
1912     int rd = bits(insn,11,15);
1913    
1914     if (!rd) return(0);
1915    
1916     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,
1917     AMD64_R15,OFFSET(cpu_mips_t,lo),8);
1918     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RDX,8);
1919     return(0);
1920     }
1921    
1922     /* MOVE (virtual instruction, real: ADDU) */
1923     DECLARE_INSN(MOVE)
1924     {
1925     int rs = bits(insn,21,25);
1926     int rd = bits(insn,11,15);
1927    
1928     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),4);
1929     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
1930     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RDX,8);
1931     return(0);
1932     }
1933    
1934     /* MTC0 */
1935     DECLARE_INSN(MTC0)
1936     {
1937     int rt = bits(insn,16,20);
1938     int rd = bits(insn,11,15);
1939    
1940     mips64_emit_cp_xfr_op(b,rt,rd,mips64_cp0_exec_mtc0);
1941     return(0);
1942     }
1943    
1944     /* MTC1 */
1945     DECLARE_INSN(MTC1)
1946     {
1947     int rt = bits(insn,16,20);
1948     int rd = bits(insn,11,15);
1949    
1950     mips64_emit_cp_xfr_op(b,rt,rd,mips64_exec_mtc1);
1951     return(0);
1952     }
1953    
1954     /* MTHI */
1955     DECLARE_INSN(MTHI)
1956     {
1957     int rs = bits(insn,21,25);
1958    
1959     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),8);
1960    
1961     amd64_mov_membase_reg(b->jit_ptr,
1962     AMD64_R15,OFFSET(cpu_mips_t,hi),AMD64_RDX,8);
1963     return(0);
1964     }
1965    
1966     /* MTLO */
1967     DECLARE_INSN(MTLO)
1968     {
1969     int rs = bits(insn,21,25);
1970    
1971     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),8);
1972    
1973     amd64_mov_membase_reg(b->jit_ptr,
1974     AMD64_R15,OFFSET(cpu_mips_t,lo),AMD64_RDX,8);
1975     return(0);
1976     }
1977    
1978     /* MUL */
1979     DECLARE_INSN(MUL)
1980     {
1981     int rs = bits(insn,21,25);
1982     int rt = bits(insn,16,20);
1983     int rd = bits(insn,11,15);
1984    
1985     /* eax = gpr[rs] */
1986     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
1987    
1988     /* ecx = gpr[rt] */
1989     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
1990    
1991     amd64_mul_reg_size(b->jit_ptr,AMD64_RCX,1,4);
1992    
1993     /* store result in gpr[rd] */
1994     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
1995     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
1996     return(0);
1997     }
1998    
1999     /* MULT */
2000     DECLARE_INSN(MULT)
2001     {
2002     int rs = bits(insn,21,25);
2003     int rt = bits(insn,16,20);
2004    
2005     /* eax = gpr[rs] */
2006     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
2007    
2008     /* ecx = gpr[rt] */
2009     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
2010    
2011     amd64_mul_reg_size(b->jit_ptr,AMD64_RCX,1,4);
2012    
2013     /* store LO */
2014     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2015     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,lo),
2016     AMD64_RAX,8);
2017    
2018     /* store HI */
2019     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
2020     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,hi),
2021     AMD64_RDX,8);
2022     return(0);
2023     }
2024    
2025     /* MULTU */
2026     DECLARE_INSN(MULTU)
2027     {
2028     int rs = bits(insn,21,25);
2029     int rt = bits(insn,16,20);
2030    
2031     /* eax = gpr[rs] */
2032     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),4);
2033    
2034     /* ecx = gpr[rt] */
2035     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rt),4);
2036    
2037     amd64_mul_reg_size(b->jit_ptr,AMD64_RCX,0,4);
2038    
2039     /* store LO */
2040     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2041     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,lo),
2042     AMD64_RAX,8);
2043    
2044     /* store HI */
2045     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RDX,X86_EDX);
2046     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,OFFSET(cpu_mips_t,hi),
2047     AMD64_RDX,8);
2048     return(0);
2049     }
2050    
2051     /* NOP */
2052     DECLARE_INSN(NOP)
2053     {
2054     return(0);
2055     }
2056    
2057     /* NOR */
2058     DECLARE_INSN(NOR)
2059     {
2060     int rs = bits(insn,21,25);
2061     int rt = bits(insn,16,20);
2062     int rd = bits(insn,11,15);
2063    
2064     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2065     amd64_alu_reg_membase(b->jit_ptr,X86_OR,AMD64_RAX,AMD64_R15,
2066     REG_OFFSET(rt));
2067     amd64_not_reg(b->jit_ptr,AMD64_RAX);
2068     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2069     return(0);
2070     }
2071    
2072     /* OR */
2073     DECLARE_INSN(OR)
2074     {
2075     int rs = bits(insn,21,25);
2076     int rt = bits(insn,16,20);
2077     int rd = bits(insn,11,15);
2078    
2079     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2080     amd64_alu_reg_membase(b->jit_ptr,X86_OR,AMD64_RAX,AMD64_R15,
2081     REG_OFFSET(rt));
2082     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2083     return(0);
2084     }
2085    
2086     /* ORI */
2087     DECLARE_INSN(ORI)
2088     {
2089     int rs = bits(insn,21,25);
2090     int rt = bits(insn,16,20);
2091     int imm = bits(insn,0,15);
2092    
2093     mips64_load_imm(b,AMD64_RAX,imm);
2094    
2095     amd64_alu_reg_membase(b->jit_ptr,X86_OR,AMD64_RAX,
2096     AMD64_R15,REG_OFFSET(rs));
2097    
2098     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RAX,8);
2099     return(0);
2100     }
2101    
2102     /* PREF */
2103     DECLARE_INSN(PREF)
2104     {
2105     amd64_nop(b->jit_ptr);
2106     return(0);
2107     }
2108    
2109     /* PREFI */
2110     DECLARE_INSN(PREFI)
2111     {
2112     amd64_nop(b->jit_ptr);
2113     return(0);
2114     }
2115    
2116     /* SB (Store Byte) */
2117     DECLARE_INSN(SB)
2118     {
2119     int base = bits(insn,21,25);
2120     int rt = bits(insn,16,20);
2121     int offset = bits(insn,0,15);
2122    
2123     mips64_emit_memop(b,MIPS_MEMOP_SB,base,offset,rt,FALSE);
2124     return(0);
2125     }
2126    
2127     /* SC (Store Conditional) */
2128     DECLARE_INSN(SC)
2129     {
2130     int base = bits(insn,21,25);
2131     int rt = bits(insn,16,20);
2132     int offset = bits(insn,0,15);
2133    
2134     mips64_emit_memop(b,MIPS_MEMOP_SC,base,offset,rt,TRUE);
2135     return(0);
2136     }
2137    
2138     /* SD (Store Double-Word) */
2139     DECLARE_INSN(SD)
2140     {
2141     int base = bits(insn,21,25);
2142     int rt = bits(insn,16,20);
2143     int offset = bits(insn,0,15);
2144    
2145     mips64_emit_memop(b,MIPS_MEMOP_SD,base,offset,rt,FALSE);
2146     return(0);
2147     }
2148    
2149     /* SDL (Store Double-Word Left) */
2150     DECLARE_INSN(SDL)
2151     {
2152     int base = bits(insn,21,25);
2153     int rt = bits(insn,16,20);
2154     int offset = bits(insn,0,15);
2155    
2156     mips64_emit_memop(b,MIPS_MEMOP_SDL,base,offset,rt,FALSE);
2157     return(0);
2158     }
2159    
2160     /* SDR (Store Double-Word Right) */
2161     DECLARE_INSN(SDR)
2162     {
2163     int base = bits(insn,21,25);
2164     int rt = bits(insn,16,20);
2165     int offset = bits(insn,0,15);
2166    
2167     mips64_emit_memop(b,MIPS_MEMOP_SDR,base,offset,rt,FALSE);
2168     return(0);
2169     }
2170    
2171     /* SDC1 (Store Double-Word from Coprocessor 1) */
2172     DECLARE_INSN(SDC1)
2173     {
2174     int base = bits(insn,21,25);
2175     int ft = bits(insn,16,20);
2176     int offset = bits(insn,0,15);
2177    
2178     mips64_emit_memop(b,MIPS_MEMOP_SDC1,base,offset,ft,FALSE);
2179     return(0);
2180     }
2181    
2182     /* SH (Store Half-Word) */
2183     DECLARE_INSN(SH)
2184     {
2185     int base = bits(insn,21,25);
2186     int rt = bits(insn,16,20);
2187     int offset = bits(insn,0,15);
2188    
2189     mips64_emit_memop(b,MIPS_MEMOP_SH,base,offset,rt,FALSE);
2190     return(0);
2191     }
2192    
2193     /* SLL */
2194     DECLARE_INSN(SLL)
2195     {
2196     int rt = bits(insn,16,20);
2197     int rd = bits(insn,11,15);
2198     int sa = bits(insn,6,10);
2199    
2200     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2201     amd64_shift_reg_imm(b->jit_ptr,X86_SHL,AMD64_RAX,sa);
2202    
2203     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2204     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2205     return(0);
2206     }
2207    
2208     /* SLLV */
2209     DECLARE_INSN(SLLV)
2210     {
2211     int rs = bits(insn,21,25);
2212     int rt = bits(insn,16,20);
2213     int rd = bits(insn,11,15);
2214    
2215     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
2216     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x1f);
2217    
2218     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2219     amd64_shift_reg(b->jit_ptr,X86_SHL,AMD64_RAX);
2220    
2221     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2222     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2223     return(0);
2224     }
2225    
2226     /* SLT */
2227     DECLARE_INSN(SLT)
2228     {
2229     int rs = bits(insn,21,25);
2230     int rt = bits(insn,16,20);
2231     int rd = bits(insn,11,15);
2232     u_char *test1;
2233    
2234     /* RDX = gpr[rs] */
2235     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),8);
2236    
2237     /* RAX = gpr[rt] */
2238     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
2239    
2240     /* we set rd to 1 when gpr[rs] < gpr[rt] */
2241     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
2242     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RCX,8);
2243    
2244     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RDX,AMD64_RAX);
2245     test1 = b->jit_ptr;
2246     amd64_branch8(b->jit_ptr, X86_CC_GE, 0, 1);
2247    
2248     amd64_inc_membase(b->jit_ptr,AMD64_R15,REG_OFFSET(rd));
2249    
2250     /* end */
2251     amd64_patch(test1,b->jit_ptr);
2252     return(0);
2253     }
2254    
2255     /* SLTI */
2256     DECLARE_INSN(SLTI)
2257     {
2258     int rs = bits(insn,21,25);
2259     int rt = bits(insn,16,20);
2260     int imm = bits(insn,0,15);
2261     m_uint64_t val = sign_extend(imm,16);
2262     u_char *test1;
2263    
2264     /* RDX = val */
2265     mips64_load_imm(b,AMD64_RDX,val);
2266    
2267     /* RAX = gpr[rs] */
2268     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2269    
2270     /* we set rt to 1 when gpr[rs] < val */
2271     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
2272     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
2273    
2274     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RDX);
2275     test1 = b->jit_ptr;
2276     amd64_branch8(b->jit_ptr, X86_CC_GE, 0, 1);
2277    
2278     amd64_inc_membase(b->jit_ptr,AMD64_R15,REG_OFFSET(rt));
2279    
2280     /* end */
2281     amd64_patch(test1,b->jit_ptr);
2282     return(0);
2283     }
2284    
2285     /* SLTU */
2286     DECLARE_INSN(SLTU)
2287     {
2288     int rs = bits(insn,21,25);
2289     int rt = bits(insn,16,20);
2290     int rd = bits(insn,11,15);
2291     u_char *test1;
2292    
2293     /* RDX = gpr[rs] */
2294     amd64_mov_reg_membase(b->jit_ptr,AMD64_RDX,AMD64_R15,REG_OFFSET(rs),8);
2295    
2296     /* RAX = gpr[rt] */
2297     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),8);
2298    
2299     /* we set rd to 1 when gpr[rs] < gpr[rt] */
2300     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
2301     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RCX,8);
2302    
2303     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RDX,AMD64_RAX);
2304     test1 = b->jit_ptr;
2305     amd64_branch8(b->jit_ptr, X86_CC_AE, 0, 0);
2306    
2307     amd64_inc_membase(b->jit_ptr,AMD64_R15,REG_OFFSET(rd));
2308    
2309     /* end */
2310     amd64_patch(test1,b->jit_ptr);
2311     return(0);
2312     }
2313    
2314     /* SLTIU */
2315     DECLARE_INSN(SLTIU)
2316     {
2317     int rs = bits(insn,21,25);
2318     int rt = bits(insn,16,20);
2319     int imm = bits(insn,0,15);
2320     m_uint64_t val = sign_extend(imm,16);
2321     u_char *test1;
2322    
2323     /* RDX = val */
2324     mips64_load_imm(b,AMD64_RDX,val);
2325    
2326     /* RAX = gpr[rs] */
2327     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2328    
2329     /* we set rt to 1 when gpr[rs] < val */
2330     amd64_clear_reg(b->jit_ptr,AMD64_RCX);
2331     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RCX,8);
2332    
2333     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RDX);
2334     test1 = b->jit_ptr;
2335     amd64_branch8(b->jit_ptr, X86_CC_AE, 0, 0);
2336    
2337     amd64_inc_membase(b->jit_ptr,AMD64_R15,REG_OFFSET(rt));
2338    
2339     /* end */
2340     amd64_patch(test1,b->jit_ptr);
2341     return(0);
2342     }
2343    
2344     /* SRA */
2345     DECLARE_INSN(SRA)
2346     {
2347     int rt = bits(insn,16,20);
2348     int rd = bits(insn,11,15);
2349     int sa = bits(insn,6,10);
2350    
2351     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2352     amd64_shift_reg_imm_size(b->jit_ptr,X86_SAR,AMD64_RAX,sa,4);
2353    
2354     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2355     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2356     return(0);
2357     }
2358    
2359     /* SRAV */
2360     DECLARE_INSN(SRAV)
2361     {
2362     int rs = bits(insn,21,25);
2363     int rt = bits(insn,16,20);
2364     int rd = bits(insn,11,15);
2365    
2366     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
2367     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x1f);
2368    
2369     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2370     amd64_shift_reg_size(b->jit_ptr,X86_SAR,AMD64_RAX,4);
2371    
2372     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2373     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2374     return(0);
2375     }
2376    
2377     /* SRL */
2378     DECLARE_INSN(SRL)
2379     {
2380     int rt = bits(insn,16,20);
2381     int rd = bits(insn,11,15);
2382     int sa = bits(insn,6,10);
2383    
2384     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2385     amd64_shift_reg_imm(b->jit_ptr,X86_SHR,AMD64_RAX,sa);
2386    
2387     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2388     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2389     return(0);
2390     }
2391    
2392     /* SRLV */
2393     DECLARE_INSN(SRLV)
2394     {
2395     int rs = bits(insn,21,25);
2396     int rt = bits(insn,16,20);
2397     int rd = bits(insn,11,15);
2398    
2399     amd64_mov_reg_membase(b->jit_ptr,AMD64_RCX,AMD64_R15,REG_OFFSET(rs),4);
2400     amd64_alu_reg_imm(b->jit_ptr,X86_AND,AMD64_RCX,0x1f);
2401    
2402     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rt),4);
2403     amd64_shift_reg(b->jit_ptr,X86_SHR,AMD64_RAX);
2404    
2405     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2406     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2407     return(0);
2408     }
2409    
2410     /* SUB */
2411     DECLARE_INSN(SUB)
2412     {
2413     int rs = bits(insn,21,25);
2414     int rt = bits(insn,16,20);
2415     int rd = bits(insn,11,15);
2416    
2417     /* TODO: Exception handling */
2418     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2419     amd64_alu_reg_membase(b->jit_ptr,X86_SUB,AMD64_RAX,AMD64_R15,
2420     REG_OFFSET(rt));
2421    
2422     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2423     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2424     return(0);
2425     }
2426    
2427     /* SUBU */
2428     DECLARE_INSN(SUBU)
2429     {
2430     int rs = bits(insn,21,25);
2431     int rt = bits(insn,16,20);
2432     int rd = bits(insn,11,15);
2433    
2434     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2435     amd64_alu_reg_membase(b->jit_ptr,X86_SUB,AMD64_RAX,AMD64_R15,
2436     REG_OFFSET(rt));
2437    
2438     amd64_movsxd_reg_reg(b->jit_ptr,AMD64_RAX,X86_EAX);
2439     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2440     return(0);
2441     }
2442    
2443     /* SW (Store Word) */
2444     DECLARE_INSN(SW)
2445     {
2446     int base = bits(insn,21,25);
2447     int rt = bits(insn,16,20);
2448     int offset = bits(insn,0,15);
2449    
2450     if (cpu->fast_memop) {
2451     mips64_emit_memop_fast(cpu,b,1,MIPS_MEMOP_SW,base,offset,rt,FALSE,
2452     mips64_memop_fast_sw);
2453     } else {
2454     mips64_emit_memop(b,MIPS_MEMOP_SW,base,offset,rt,FALSE);
2455     }
2456     return(0);
2457     }
2458    
2459     /* SWL (Store Word Left) */
2460     DECLARE_INSN(SWL)
2461     {
2462     int base = bits(insn,21,25);
2463     int rt = bits(insn,16,20);
2464     int offset = bits(insn,0,15);
2465    
2466     mips64_emit_memop(b,MIPS_MEMOP_SWL,base,offset,rt,FALSE);
2467     return(0);
2468     }
2469    
2470     /* SWR (Store Word Right) */
2471     DECLARE_INSN(SWR)
2472     {
2473     int base = bits(insn,21,25);
2474     int rt = bits(insn,16,20);
2475     int offset = bits(insn,0,15);
2476    
2477     mips64_emit_memop(b,MIPS_MEMOP_SWR,base,offset,rt,FALSE);
2478     return(0);
2479     }
2480    
2481     /* SYNC */
2482     DECLARE_INSN(SYNC)
2483     {
2484     return(0);
2485     }
2486    
2487     /* SYSCALL */
2488     DECLARE_INSN(SYSCALL)
2489     {
2490     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2491     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2492     mips64_emit_basic_c_call(b,mips64_exec_syscall);
2493     mips64_jit_tcb_push_epilog(b);
2494     return(0);
2495     }
2496    
2497     /* TEQ (Trap If Equal) */
2498     DECLARE_INSN(TEQ)
2499     {
2500     int rs = bits(insn,21,25);
2501     int rt = bits(insn,16,20);
2502     u_char *test1;
2503    
2504     /*
2505     * compare gpr[rs] and gpr[rt].
2506     */
2507     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2508     amd64_alu_reg_membase(b->jit_ptr,X86_CMP,AMD64_RAX,
2509     AMD64_R15,REG_OFFSET(rt));
2510     test1 = b->jit_ptr;
2511     amd64_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
2512    
2513     /* Generate trap exception */
2514     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2515     mips64_emit_c_call(b,mips64_trigger_trap_exception);
2516     mips64_jit_tcb_push_epilog(b);
2517    
2518     /* end */
2519     amd64_patch(test1,b->jit_ptr);
2520     return(0);
2521     }
2522    
2523     /* TEQI (Trap If Equal Immediate) */
2524     DECLARE_INSN(TEQI)
2525     {
2526     int rs = bits(insn,21,25);
2527     int imm = bits(insn,0,15);
2528     m_uint64_t val = sign_extend(imm,16);
2529     u_char *test1;
2530    
2531     /* RDX = val */
2532     mips64_load_imm(b,AMD64_RDX,val);
2533    
2534     /* RAX = gpr[rs] */
2535     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2536    
2537     amd64_alu_reg_reg(b->jit_ptr,X86_CMP,AMD64_RAX,AMD64_RDX);
2538     test1 = b->jit_ptr;
2539     amd64_branch8(b->jit_ptr, X86_CC_NE, 0, 1);
2540    
2541     /* Generate trap exception */
2542     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2543     mips64_emit_c_call(b,mips64_trigger_trap_exception);
2544     mips64_jit_tcb_push_epilog(b);
2545    
2546     /* end */
2547     amd64_patch(test1,b->jit_ptr);
2548     return(0);
2549     }
2550    
2551     /* TLBP */
2552     DECLARE_INSN(TLBP)
2553     {
2554     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2555     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2556     mips64_emit_basic_c_call(b,mips64_cp0_exec_tlbp);
2557     return(0);
2558     }
2559    
2560     /* TLBR */
2561     DECLARE_INSN(TLBR)
2562     {
2563     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2564     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2565     mips64_emit_basic_c_call(b,mips64_cp0_exec_tlbr);
2566     return(0);
2567     }
2568    
2569     /* TLBWI */
2570     DECLARE_INSN(TLBWI)
2571     {
2572     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2573     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2574     mips64_emit_basic_c_call(b,mips64_cp0_exec_tlbwi);
2575     return(0);
2576     }
2577    
2578     /* TLBWR */
2579     DECLARE_INSN(TLBWR)
2580     {
2581     mips64_set_pc(b,b->start_pc+((b->mips_trans_pos-1)<<2));
2582     amd64_mov_reg_reg(b->jit_ptr,AMD64_RDI,AMD64_R15,8);
2583     mips64_emit_basic_c_call(b,mips64_cp0_exec_tlbwr);
2584     return(0);
2585     }
2586    
2587     /* XOR */
2588     DECLARE_INSN(XOR)
2589     {
2590     int rs = bits(insn,21,25);
2591     int rt = bits(insn,16,20);
2592     int rd = bits(insn,11,15);
2593    
2594     amd64_mov_reg_membase(b->jit_ptr,AMD64_RAX,AMD64_R15,REG_OFFSET(rs),8);
2595     amd64_alu_reg_membase(b->jit_ptr,X86_XOR,AMD64_RAX,AMD64_R15,
2596     REG_OFFSET(rt));
2597     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rd),AMD64_RAX,8);
2598     return(0);
2599     }
2600    
2601     /* XORI */
2602     DECLARE_INSN(XORI)
2603     {
2604     int rs = bits(insn,21,25);
2605     int rt = bits(insn,16,20);
2606     int imm = bits(insn,0,15);
2607    
2608     mips64_load_imm(b,AMD64_RAX,imm);
2609    
2610     amd64_alu_reg_membase(b->jit_ptr,X86_XOR,AMD64_RAX,
2611     AMD64_R15,REG_OFFSET(rs));
2612    
2613     amd64_mov_membase_reg(b->jit_ptr,AMD64_R15,REG_OFFSET(rt),AMD64_RAX,8);
2614     return(0);
2615     }
2616    
2617     /* MIPS instruction array */
2618     struct mips64_insn_tag mips64_insn_tags[] = {
2619     { mips64_emit_LI , 0xffe00000 , 0x24000000, 1 }, /* virtual */
2620     { mips64_emit_MOVE , 0xfc1f07ff , 0x00000021, 1 }, /* virtual */
2621     { mips64_emit_B , 0xffff0000 , 0x10000000, 0 }, /* virtual */
2622     { mips64_emit_BAL , 0xffff0000 , 0x04110000, 0 }, /* virtual */
2623     { mips64_emit_BEQZ , 0xfc1f0000 , 0x10000000, 0 }, /* virtual */
2624     { mips64_emit_BNEZ , 0xfc1f0000 , 0x14000000, 0 }, /* virtual */
2625     { mips64_emit_ADD , 0xfc0007ff , 0x00000020, 1 },
2626     { mips64_emit_ADDI , 0xfc000000 , 0x20000000, 1 },
2627     { mips64_emit_ADDIU , 0xfc000000 , 0x24000000, 1 },
2628     { mips64_emit_ADDU , 0xfc0007ff , 0x00000021, 1 },
2629     { mips64_emit_AND , 0xfc0007ff , 0x00000024, 1 },
2630     { mips64_emit_ANDI , 0xfc000000 , 0x30000000, 1 },
2631     { mips64_emit_BEQ , 0xfc000000 , 0x10000000, 0 },
2632     { mips64_emit_BEQL , 0xfc000000 , 0x50000000, 0 },
2633     { mips64_emit_BGEZ , 0xfc1f0000 , 0x04010000, 0 },
2634     { mips64_emit_BGEZAL , 0xfc1f0000 , 0x04110000, 0 },
2635     { mips64_emit_BGEZALL , 0xfc1f0000 , 0x04130000, 0 },
2636     { mips64_emit_BGEZL , 0xfc1f0000 , 0x04030000, 0 },
2637     { mips64_emit_BGTZ , 0xfc1f0000 , 0x1c000000, 0 },
2638     { mips64_emit_BGTZL , 0xfc1f0000 , 0x5c000000, 0 },
2639     { mips64_emit_BLEZ , 0xfc1f0000 , 0x18000000, 0 },
2640     { mips64_emit_BLEZL , 0xfc1f0000 , 0x58000000, 0 },
2641     { mips64_emit_BLTZ , 0xfc1f0000 , 0x04000000, 0 },
2642     { mips64_emit_BLTZAL , 0xfc1f0000 , 0x04100000, 0 },
2643     { mips64_emit_BLTZALL , 0xfc1f0000 , 0x04120000, 0 },
2644     { mips64_emit_BLTZL , 0xfc1f0000 , 0x04020000, 0 },
2645     { mips64_emit_BNE , 0xfc000000 , 0x14000000, 0 },
2646     { mips64_emit_BNEL , 0xfc000000 , 0x54000000, 0 },
2647     { mips64_emit_BREAK , 0xfc00003f , 0x0000000d, 1 },
2648     { mips64_emit_CACHE , 0xfc000000 , 0xbc000000, 1 },
2649     { mips64_emit_CFC0 , 0xffe007ff , 0x40400000, 1 },
2650     { mips64_emit_CTC0 , 0xffe007ff , 0x40600000, 1 },
2651     { mips64_emit_DADDIU , 0xfc000000 , 0x64000000, 1 },
2652     { mips64_emit_DADDU , 0xfc0007ff , 0x0000002d, 1 },
2653     { mips64_emit_DIV , 0xfc00ffff , 0x0000001a, 1 },
2654     { mips64_emit_DIVU , 0xfc00ffff , 0x0000001b, 1 },
2655     { mips64_emit_DMFC0 , 0xffe007f8 , 0x40200000, 1 },
2656     { mips64_emit_DMFC1 , 0xffe007ff , 0x44200000, 1 },
2657     { mips64_emit_DMTC0 , 0xffe007f8 , 0x40a00000, 1 },
2658     { mips64_emit_DMTC1 , 0xffe007ff , 0x44a00000, 1 },
2659     { mips64_emit_DSLL , 0xffe0003f , 0x00000038, 1 },
2660     { mips64_emit_DSLL32 , 0xffe0003f , 0x0000003c, 1 },
2661     { mips64_emit_DSLLV , 0xfc0007ff , 0x00000014, 1 },
2662     { mips64_emit_DSRA , 0xffe0003f , 0x0000003b, 1 },
2663     { mips64_emit_DSRA32 , 0xffe0003f , 0x0000003f, 1 },
2664     { mips64_emit_DSRAV , 0xfc0007ff , 0x00000017, 1 },
2665     { mips64_emit_DSRL , 0xffe0003f , 0x0000003a, 1 },
2666     { mips64_emit_DSRL32 , 0xffe0003f , 0x0000003e, 1 },
2667     { mips64_emit_DSRLV , 0xfc0007ff , 0x00000016, 1 },
2668     { mips64_emit_DSUBU , 0xfc0007ff , 0x0000002f, 1 },
2669     { mips64_emit_ERET , 0xffffffff , 0x42000018, 0 },
2670     { mips64_emit_J , 0xfc000000 , 0x08000000, 0 },
2671     { mips64_emit_JAL , 0xfc000000 , 0x0c000000, 0 },
2672     { mips64_emit_JALR , 0xfc1f003f , 0x00000009, 0 },
2673     { mips64_emit_JR , 0xfc1ff83f , 0x00000008, 0 },
2674     { mips64_emit_LB , 0xfc000000 , 0x80000000, 1 },
2675     { mips64_emit_LBU , 0xfc000000 , 0x90000000, 1 },
2676     { mips64_emit_LD , 0xfc000000 , 0xdc000000, 1 },
2677     { mips64_emit_LDC1 , 0xfc000000 , 0xd4000000, 1 },
2678     { mips64_emit_LDL , 0xfc000000 , 0x68000000, 1 },
2679     { mips64_emit_LDR , 0xfc000000 , 0x6c000000, 1 },
2680     { mips64_emit_LH , 0xfc000000 , 0x84000000, 1 },
2681     { mips64_emit_LHU , 0xfc000000 , 0x94000000, 1 },
2682     { mips64_emit_LL , 0xfc000000 , 0xc0000000, 1 },
2683     { mips64_emit_LUI , 0xffe00000 , 0x3c000000, 1 },
2684     { mips64_emit_LW , 0xfc000000 , 0x8c000000, 1 },
2685     { mips64_emit_LWL , 0xfc000000 , 0x88000000, 1 },
2686     { mips64_emit_LWR , 0xfc000000 , 0x98000000, 1 },
2687     { mips64_emit_LWU , 0xfc000000 , 0x9c000000, 1 },
2688     { mips64_emit_MFC0 , 0xffe007ff , 0x40000000, 1 },
2689     { mips64_emit_CFC0 , 0xffe007ff , 0x40000001, 1 }, /* MFC0 / Set 1 */
2690     { mips64_emit_MFC1 , 0xffe007ff , 0x44000000, 1 },
2691     { mips64_emit_MFHI , 0xffff07ff , 0x00000010, 1 },
2692     { mips64_emit_MFLO , 0xffff07ff , 0x00000012, 1 },
2693     { mips64_emit_MTC0 , 0xffe007ff , 0x40800000, 1 },
2694     { mips64_emit_MTC1 , 0xffe007ff , 0x44800000, 1 },
2695     { mips64_emit_MTHI , 0xfc1fffff , 0x00000011, 1 },
2696     { mips64_emit_MTLO , 0xfc1fffff , 0x00000013, 1 },
2697     { mips64_emit_MUL , 0xfc0007ff , 0x70000002, 1 },
2698     { mips64_emit_MULT , 0xfc00ffff , 0x00000018, 1 },
2699     { mips64_emit_MULTU , 0xfc00ffff , 0x00000019, 1 },
2700     { mips64_emit_NOP , 0xffffffff , 0x00000000, 1 },
2701     { mips64_emit_NOR , 0xfc0007ff , 0x00000027, 1 },
2702     { mips64_emit_OR , 0xfc0007ff , 0x00000025, 1 },
2703     { mips64_emit_ORI , 0xfc000000 , 0x34000000, 1 },
2704     { mips64_emit_PREF , 0xfc000000 , 0xcc000000, 1 },
2705     { mips64_emit_PREFI , 0xfc0007ff , 0x4c00000f, 1 },
2706     { mips64_emit_SB , 0xfc000000 , 0xa0000000, 1 },
2707     { mips64_emit_SC , 0xfc000000 , 0xe0000000, 1 },
2708     { mips64_emit_SD , 0xfc000000 , 0xfc000000, 1 },
2709     { mips64_emit_SDC1 , 0xfc000000 , 0xf4000000, 1 },
2710     { mips64_emit_SDL , 0xfc000000 , 0xb0000000, 1 },
2711     { mips64_emit_SDR , 0xfc000000 , 0xb4000000, 1 },
2712     { mips64_emit_SH , 0xfc000000 , 0xa4000000, 1 },
2713     { mips64_emit_SLL , 0xffe0003f , 0x00000000, 1 },
2714     { mips64_emit_SLLV , 0xfc0007ff , 0x00000004, 1 },
2715     { mips64_emit_SLT , 0xfc0007ff , 0x0000002a, 1 },
2716     { mips64_emit_SLTI , 0xfc000000 , 0x28000000, 1 },
2717     { mips64_emit_SLTIU , 0xfc000000 , 0x2c000000, 1 },
2718     { mips64_emit_SLTU , 0xfc0007ff , 0x0000002b, 1 },
2719     { mips64_emit_SRA , 0xffe0003f , 0x00000003, 1 },
2720     { mips64_emit_SRAV , 0xfc0007ff , 0x00000007, 1 },
2721     { mips64_emit_SRL , 0xffe0003f , 0x00000002, 1 },
2722     { mips64_emit_SRLV , 0xfc0007ff , 0x00000006, 1 },
2723     { mips64_emit_SUB , 0xfc0007ff , 0x00000022, 1 },
2724     { mips64_emit_SUBU , 0xfc0007ff , 0x00000023, 1 },
2725     { mips64_emit_SW , 0xfc000000 , 0xac000000, 1 },
2726     { mips64_emit_SWL , 0xfc000000 , 0xa8000000, 1 },
2727     { mips64_emit_SWR , 0xfc000000 , 0xb8000000, 1 },
2728     { mips64_emit_SYNC , 0xfffff83f , 0x0000000f, 1 },
2729     { mips64_emit_SYSCALL , 0xfc00003f , 0x0000000c, 1 },
2730     { mips64_emit_TEQ , 0xfc00003f , 0x00000034, 1 },
2731     { mips64_emit_TEQI , 0xfc1f0000 , 0x040c0000, 1 },
2732     { mips64_emit_TLBP , 0xffffffff , 0x42000008, 1 },
2733     { mips64_emit_TLBR , 0xffffffff , 0x42000001, 1 },
2734     { mips64_emit_TLBWI , 0xffffffff , 0x42000002, 1 },
2735     { mips64_emit_TLBWR , 0xffffffff , 0x42000006, 1 },
2736     { mips64_emit_XOR , 0xfc0007ff , 0x00000026, 1 },
2737     { mips64_emit_XORI , 0xfc000000 , 0x38000000, 1 },
2738     { mips64_emit_unknown , 0x00000000 , 0x00000000, 1 },
2739 dpavlin 8 { NULL , 0x00000000 , 0x00000000, 0 },
2740 dpavlin 7 };
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