/[dynamips]/trunk/dev_sb1_pci.c
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Contents of /trunk/dev_sb1_pci.c

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Revision 8 - (show annotations)
Sat Oct 6 16:24:54 2007 UTC (11 years, 8 months ago) by dpavlin
Original Path: upstream/dynamips-0.2.7-RC2/dev_sb1_pci.c
File MIME type: text/plain
File size: 3873 byte(s)
dynamips-0.2.7-RC2

1 /*
2 * Cisco router simulation platform.
3 * Copyright (c) 2006 Christophe Fillot. All rights reserved.
4 *
5 * PCI configuration space for SB-1 processor.
6 */
7
8 #include <stdio.h>
9 #include <stdlib.h>
10 #include <string.h>
11 #include <time.h>
12 #include <errno.h>
13
14 #include "cpu.h"
15 #include "vm.h"
16 #include "dynamips.h"
17 #include "memory.h"
18 #include "device.h"
19
20 #define DEBUG_ACCESS 0
21
22 /* Sibyte PCI ID */
23 #define SB1_PCI_VENDOR_ID 0x166D
24
25 /* SB-1 PCI private data */
26 struct sb1_pci_data {
27 vm_obj_t vm_obj;
28 struct vdevice dev;
29 struct pci_bus *pci_bus;
30
31 /* PCI configuration (Bus 0, Device 0) */
32 struct pci_device *pci_cfg_dev;
33
34 /* HyperTransport configuration (Bus 0, Device 1) */
35 struct pci_device *ht_cfg_dev;
36 };
37
38 /*
39 * sb1_pci_cfg_read()
40 *
41 * PCI Configuration (Bus 0, Device 0).
42 */
43 static m_uint32_t sb1_pci_cfg_read(cpu_gen_t *cpu,struct pci_device *dev,
44 int reg)
45 {
46 switch(reg) {
47 case 0x08:
48 return(0x06000002);
49 default:
50 return(0);
51 }
52 }
53
54 /*
55 * sb1_ht_cfg_read()
56 *
57 * HyperTransport Configuration (Bus 0, Device 1).
58 */
59 static m_uint32_t sb1_ht_cfg_read(cpu_gen_t *cpu,struct pci_device *dev,
60 int reg)
61 {
62 switch(reg) {
63 case 0x08:
64 return(0x06000002);
65 case 0x44:
66 return(1<<5); /* HyperTransport OK */
67 default:
68 return(0);
69 }
70 }
71
72 /*
73 * dev_sb1_pci_access()
74 */
75 void *dev_sb1_pci_access(cpu_gen_t *cpu,struct vdevice *dev,
76 m_uint32_t offset,u_int op_size,u_int op_type,
77 m_uint64_t *data)
78 {
79 struct sb1_pci_data *d = dev->priv_data;
80
81 #if DEBUG_ACCESS
82 if (op_type == MTS_READ)
83 cpu_log(cpu,dev->name,"read access to offset = 0x%x, pc = 0x%llx\n",
84 offset,cpu_get_pc(cpu));
85 else
86 cpu_log(cpu,dev->name,"write access to vaddr = 0x%x, pc = 0x%llx, "
87 "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data);
88 #endif
89
90 if (op_type == MTS_READ)
91 *data = 0;
92
93 d->pci_bus->pci_addr = offset;
94 pci_dev_data_handler(cpu,d->pci_bus,op_type,FALSE,data);
95 return NULL;
96 }
97
98 /* Shutdown the PCI bus configuration zone */
99 void dev_sb1_pci_shutdown(vm_instance_t *vm,struct sb1_pci_data *d)
100 {
101 if (d != NULL) {
102 /* Remove the device */
103 dev_remove(vm,&d->dev);
104
105 /* Free the structure itself */
106 free(d);
107 }
108 }
109
110 /* Create the SB-1 PCI bus configuration zone */
111 int dev_sb1_pci_init(vm_instance_t *vm,char *name,m_uint64_t paddr)
112 {
113 struct sb1_pci_data *d;
114
115 /* allocate the private data structure */
116 if (!(d = malloc(sizeof(*d)))) {
117 fprintf(stderr,"SB1_PCI: unable to create device.\n");
118 return(-1);
119 }
120
121 memset(d,0,sizeof(*d));
122 d->pci_bus = vm->pci_bus[0];
123
124 vm_object_init(&d->vm_obj);
125 d->vm_obj.name = name;
126 d->vm_obj.data = d;
127 d->vm_obj.shutdown = (vm_shutdown_t)dev_sb1_pci_shutdown;
128
129 dev_init(&d->dev);
130 d->dev.name = name;
131 d->dev.priv_data = d;
132 d->dev.phys_addr = paddr;
133 d->dev.phys_len = 1 << 24;
134 d->dev.handler = dev_sb1_pci_access;
135
136 /* PCI configuration header on Bus 0, Device 0 */
137 d->pci_cfg_dev = pci_dev_add(d->pci_bus,"sb1_pci_cfg",
138 SB1_PCI_VENDOR_ID,0x0001,0,0,-1,NULL,
139 NULL,sb1_pci_cfg_read,NULL);
140
141 /* Create the HyperTransport bus #1 */
142 vm->pci_bus_pool[28] = pci_bus_create("HT bus #1",-1);
143
144 /* HyperTransport configuration header on Bus 0, Device 1 */
145 d->ht_cfg_dev = pci_bridge_create_dev(d->pci_bus,"sb1_ht_cfg",
146 SB1_PCI_VENDOR_ID,0x0002,
147 1,0,vm->pci_bus_pool[28],
148 sb1_ht_cfg_read,NULL);
149
150 /* Map this device to the VM */
151 vm_bind_device(vm,&d->dev);
152 vm_object_add(vm,&d->vm_obj);
153 return(0);
154 }

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