/[dynamips]/trunk/dev_pa_mc8te1.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.6-RC5/dev_pa_mc8te1.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7-RC3/dev_pa_mc8te1.c revision 9 by dpavlin, Sat Oct 6 16:26:06 2007 UTC
# Line 1  Line 1 
1  /*    /*  
2   * Cisco C7200 (Predator) Simulation Platform.   * Cisco router simulation platform.
3   * Copyright (C) 2005-2006 Christophe Fillot.  All rights reserved.   * Copyright (C) 2005-2006 Christophe Fillot.  All rights reserved.
4   *   *
5   * PA-MC-8TE1 card. Doesn't work at this time.   * PA-MC-8TE1 card. Doesn't work at this time.
# Line 13  Line 13 
13  #include <pthread.h>  #include <pthread.h>
14  #include <assert.h>  #include <assert.h>
15    
16  #include "mips64.h"  #include "cpu.h"
17    #include "vm.h"
18  #include "dynamips.h"  #include "dynamips.h"
19  #include "memory.h"  #include "memory.h"
20  #include "device.h"  #include "device.h"
# Line 36  Line 37 
37  /* PA-MC-8TE1 Data */  /* PA-MC-8TE1 Data */
38  struct pa_mc_data {  struct pa_mc_data {
39     char *name;     char *name;
40       u_int irq;
41    
42     /* Virtual machine */     /* Virtual machine */
43     vm_instance_t *vm;     vm_instance_t *vm;
# Line 50  struct pa_mc_data { Line 52  struct pa_mc_data {
52     m_uint8_t ssram_data[0x20000];     m_uint8_t ssram_data[0x20000];
53    
54     /* PLX9054 */     /* PLX9054 */
55       char *plx_name;
56     vm_obj_t *plx_obj;     vm_obj_t *plx_obj;
57    
58     /* NetIO descriptor */     /* NetIO descriptor */
# Line 65  struct pa_mc_data { Line 68  struct pa_mc_data {
68  /*  /*
69   * dev_ssram_access   * dev_ssram_access
70   */   */
71  static void *dev_ssram_access(cpu_mips_t *cpu,struct vdevice *dev,  static void *dev_ssram_access(cpu_gen_t *cpu,struct vdevice *dev,
72                                m_uint32_t offset,u_int op_size,u_int op_type,                                m_uint32_t offset,u_int op_size,u_int op_type,
73                                m_uint64_t *data)                                m_uint64_t *data)
74  {  {
# Line 81  static void *dev_ssram_access(cpu_mips_t Line 84  static void *dev_ssram_access(cpu_mips_t
84     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
85        cpu_log(cpu,d->name,        cpu_log(cpu,d->name,
86                "read  access to offset = 0x%x, pc = 0x%llx (size=%u)\n",                "read  access to offset = 0x%x, pc = 0x%llx (size=%u)\n",
87                offset,cpu->pc,op_size);                offset,cpu_get_pc(cpu),op_size);
88     } else {     } else {
89        cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "        cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "
90                "val = 0x%llx (size=%u)\n",offset,cpu->pc,*data,op_size);                "val = 0x%llx (size=%u)\n",
91                  offset,cpu_get_pc(cpu),*data,op_size);
92     }     }
93  #endif  #endif
94    
# Line 133  static void plx9054_doorbell_callback(st Line 137  static void plx9054_doorbell_callback(st
137     printf("DOORBELL: 0x%x\n",val);     printf("DOORBELL: 0x%x\n",val);
138    
139     /* Trigger interrupt */     /* Trigger interrupt */
140     vm_set_irq(pa_data->vm,2);     //vm_set_irq(pa_data->vm,pa_data->irq);
141     vm_set_irq(pa_data->vm,3);     vm_set_irq(pa_data->vm,3);
142  }  }
143    
144  /*  /*
145   * pa_mc8te1_access()   * pa_mc8te1_access()
146   */   */
147  static void *pa_mc8te1_access(cpu_mips_t *cpu,struct vdevice *dev,  static void *pa_mc8te1_access(cpu_gen_t *cpu,struct vdevice *dev,
148                                m_uint32_t offset,u_int op_size,u_int op_type,                                m_uint32_t offset,u_int op_size,u_int op_type,
149                                m_uint64_t *data)                                m_uint64_t *data)
150  {  {
# Line 152  static void *pa_mc8te1_access(cpu_mips_t Line 156  static void *pa_mc8te1_access(cpu_mips_t
156  #if DEBUG_ACCESS  #if DEBUG_ACCESS
157     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
158        cpu_log(cpu,d->name,"read  access to offset = 0x%x, pc = 0x%llx\n",        cpu_log(cpu,d->name,"read  access to offset = 0x%x, pc = 0x%llx\n",
159                offset,cpu->pc);                offset,cpu_get_pc(cpu));
160     } else {     } else {
161        cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "        cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "
162                "val = 0x%llx\n",offset,cpu->pc,*data);                "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data);
163     }     }
164  #endif  #endif
165    
# Line 166  static void *pa_mc8te1_access(cpu_mips_t Line 170  static void *pa_mc8te1_access(cpu_mips_t
170           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
171              cpu_log(cpu,d->name,              cpu_log(cpu,d->name,
172                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",                      "read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
173                      offset,cpu->pc,op_size);                      offset,cpu_get_pc(cpu),op_size);
174           } else {           } else {
175              cpu_log(cpu,d->name,              cpu_log(cpu,d->name,
176                      "write to unknown addr 0x%x, value=0x%llx, "                      "write to unknown addr 0x%x, value=0x%llx, "
177                      "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                      "pc=0x%llx (size=%u)\n",
178                        offset,*data,cpu_get_pc(cpu),op_size);
179           }           }
180  #endif  #endif
181     }     }
# Line 181  static void *pa_mc8te1_access(cpu_mips_t Line 186  static void *pa_mc8te1_access(cpu_mips_t
186  /*  /*
187   * pci_pos_read()   * pci_pos_read()
188   */   */
189  static m_uint32_t pci_pos_read(cpu_mips_t *cpu,struct pci_device *dev,int reg)  static m_uint32_t pci_pos_read(cpu_gen_t *cpu,struct pci_device *dev,int reg)
190  {  {
191     struct pa_mc_data *d = dev->priv_data;     struct pa_mc_data *d = dev->priv_data;
192    
# Line 200  static m_uint32_t pci_pos_read(cpu_mips_ Line 205  static m_uint32_t pci_pos_read(cpu_mips_
205  /*  /*
206   * pci_pos_write()   * pci_pos_write()
207   */   */
208  static void pci_pos_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_pos_write(cpu_gen_t *cpu,struct pci_device *dev,
209                            int reg,m_uint32_t value)                            int reg,m_uint32_t value)
210  {  {
211     struct pa_mc_data *d = dev->priv_data;     struct pa_mc_data *d = dev->priv_data;
# Line 235  int dev_c7200_pa_mc8te1_init(c7200_t *ro Line 240  int dev_c7200_pa_mc8te1_init(c7200_t *ro
240     memset(d,0,sizeof(*d));     memset(d,0,sizeof(*d));
241     d->name = name;     d->name = name;
242     d->vm   = router->vm;     d->vm   = router->vm;
243       d->irq  = c7200_net_irq_for_slot_port(pa_bay,0);
244    
245     /* Set the EEPROM */     /* Set the EEPROM */
246     c7200_pa_set_eeprom(router,pa_bay,cisco_eeprom_find_pa("PA-MC-8TE1"));     c7200_pa_set_eeprom(router,pa_bay,cisco_eeprom_find_pa("PA-MC-8TE1"));
# Line 242  int dev_c7200_pa_mc8te1_init(c7200_t *ro Line 248  int dev_c7200_pa_mc8te1_init(c7200_t *ro
248     /* Create the PM7380 */     /* Create the PM7380 */
249     d->pci_dev = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,     d->pci_dev = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,
250                              0x11f8, 0x7380,                              0x11f8, 0x7380,
251                              0,0,C7200_NETIO_IRQ,d,                              0,0,d->irq,d,
252                              NULL,pci_pos_read,pci_pos_write);                              NULL,pci_pos_read,pci_pos_write);
253    
254     /* Initialize SSRAM device */     /* Initialize SSRAM device */
# Line 253  int dev_c7200_pa_mc8te1_init(c7200_t *ro Line 259  int dev_c7200_pa_mc8te1_init(c7200_t *ro
259     d->ssram_dev.handler   = dev_ssram_access;     d->ssram_dev.handler   = dev_ssram_access;
260    
261     /* Create the PLX9054 */     /* Create the PLX9054 */
262     d->plx_obj = dev_plx9054_init(d->vm,d->name,     d->plx_name = dyn_sprintf("%s_plx",name);
263       d->plx_obj = dev_plx9054_init(d->vm,d->plx_name,
264                                   router->pa_bay[pa_bay].pci_map,1,                                   router->pa_bay[pa_bay].pci_map,1,
265                                   &d->ssram_dev,NULL);                                   &d->ssram_dev,NULL);
266    
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