/[dynamips]/trunk/dev_pa_a1.c
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upstream/dynamips-0.2.6-RC1/dev_pa_a1.c revision 2 by dpavlin, Sat Oct 6 16:03:58 2007 UTC upstream/dynamips-0.2.7/dev_pa_a1.c revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC
# Line 1  Line 1 
1  /*    /*  
2   * Cisco C7200 (Predator) Simulation Platform.   * Cisco router simulation platform.
3   * Copyright (C) 2005,2006 Christophe Fillot.  All rights reserved.   * Copyright (C) 2005,2006 Christophe Fillot.  All rights reserved.
4   *   *
5   * PA-A1 ATM interface based on TI1570 and PLX 9060-ES.   * PA-A1 ATM interface based on TI1570 and PLX 9060-ES.
# Line 35  Line 35 
35    
36  #include "crc.h"  #include "crc.h"
37  #include "atm.h"  #include "atm.h"
38  #include "mips64.h"  #include "cpu.h"
39    #include "vm.h"
40  #include "dynamips.h"  #include "dynamips.h"
41  #include "memory.h"  #include "memory.h"
42  #include "device.h"  #include "device.h"
# Line 284  struct ti1570_rcr_entry { Line 285  struct ti1570_rcr_entry {
285  struct pa_a1_data {  struct pa_a1_data {
286     char *name;     char *name;
287    
288       /* IRQ clearing counter */
289       u_int irq_clear_count;
290    
291     /* Control Memory pointer */     /* Control Memory pointer */
292     m_uint32_t *ctrl_mem_ptr;     m_uint32_t *ctrl_mem_ptr;
293    
# Line 329  struct pa_a1_data { Line 333  struct pa_a1_data {
333     ptask_id_t tx_tid;     ptask_id_t tx_tid;
334  };  };
335    
 /* EEPROM definition */  
 static const m_uint16_t eeprom_pa_a1_data[64] = {  
    0x0117, 0x010F, 0xffff, 0xffff, 0x4906, 0x2E07, 0x0000, 0x0000,  
    0x5000, 0x0000, 0x0010, 0x2400, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,  
 };  
   
 static const struct c7200_eeprom eeprom_pa_a1 = {  
    "PA-A1-OC3MM", (m_uint16_t *)eeprom_pa_a1_data, sizeof(eeprom_pa_a1_data)/2,  
 };  
   
336  /* Log a TI1570 message */  /* Log a TI1570 message */
337  #define TI1570_LOG(d,msg...) vm_log((d)->vm,(d)->name,msg)  #define TI1570_LOG(d,msg...) vm_log((d)->vm,(d)->name,msg)
338    
339  /* Reset the TI1570 (forward declaration) */  /* Reset the TI1570 (forward declaration) */
340  static void ti1570_reset(struct pa_a1_data *d,int clear_ctrl_mem);  static void ti1570_reset(struct pa_a1_data *d,int clear_ctrl_mem);
341    
342    /* Update the interrupt status */
343    static inline void dev_pa_a1_update_irq_status(struct pa_a1_data *d)
344    {
345       if (d->iregs[TI1570_REG_STATUS] & d->iregs[TI1570_REG_IMASK]) {
346          pci_dev_trigger_irq(d->vm,d->pci_dev_ti);
347       } else {
348          pci_dev_clear_irq(d->vm,d->pci_dev_ti);
349       }
350    }
351    
352  /*  /*
353   * dev_pa_a1_access()   * dev_pa_a1_access()
354   */   */
355  void *dev_pa_a1_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *dev_pa_a1_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
356                         u_int op_size,u_int op_type,m_uint64_t *data)                         u_int op_size,u_int op_type,m_uint64_t *data)
357  {  {
358     struct pa_a1_data *d = dev->priv_data;     struct pa_a1_data *d = dev->priv_data;
# Line 359  void *dev_pa_a1_access(cpu_mips_t *cpu,s Line 363  void *dev_pa_a1_access(cpu_mips_t *cpu,s
363  #if DEBUG_ACCESS  #if DEBUG_ACCESS
364     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
365        cpu_log(cpu,"TI1570","read  access to offset = 0x%x, pc = 0x%llx\n",        cpu_log(cpu,"TI1570","read  access to offset = 0x%x, pc = 0x%llx\n",
366                offset,cpu->pc);                offset,cpu_get_pc(cpu));
367     } else {     } else {
368        cpu_log(cpu,"TI1570","write access to vaddr = 0x%x, pc = 0x%llx, "        cpu_log(cpu,"TI1570","write access to vaddr = 0x%x, pc = 0x%llx, "
369                "val = 0x%llx\n",offset,cpu->pc,*data);                "val = 0x%llx\n",offset,cpu_get_pc(cpu),*data);
370     }     }
371  #endif    #endif  
372    
373     /* Specific cases */     /* Specific cases */
374     switch(offset) {     switch(offset) {
375          /* Status register */
376          case 0x3204:
377             if (op_type == MTS_READ) {
378                *data = d->iregs[TI1570_REG_STATUS];
379    
380                if (++d->irq_clear_count == 2) {
381                   d->iregs[TI1570_REG_STATUS] &= ~0x3FF;
382                   d->irq_clear_count = 0;
383                }
384    
385                dev_pa_a1_update_irq_status(d);
386             }
387             break;
388    
389          /* Software Reset register */
390        case 0x3238:        case 0x3238:
391           TI1570_LOG(d,"reset issued.\n");           TI1570_LOG(d,"reset issued.\n");
392           ti1570_reset(d,FALSE);           ti1570_reset(d,FALSE);
# Line 394  void *dev_pa_a1_access(cpu_mips_t *cpu,s Line 413  void *dev_pa_a1_access(cpu_mips_t *cpu,s
413  #if DEBUG_UNKNOWN  #if DEBUG_UNKNOWN
414     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
415        cpu_log(cpu,d->name,"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",        cpu_log(cpu,d->name,"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n",
416                offset,cpu->pc,op_size);                offset,cpu_get_pc(cpu),op_size);
417     } else {     } else {
418        cpu_log(cpu,d->name,"write to unknown addr 0x%x, value=0x%llx, "        cpu_log(cpu,d->name,"write to unknown addr 0x%x, value=0x%llx, "
419                "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);                "pc=0x%llx (size=%u)\n",offset,*data,cpu_get_pc(cpu),op_size);
420     }     }
421  #endif  #endif
422     return NULL;     return NULL;
# Line 897  static int ti1570_scan_tx_dma_entry_sing Line 916  static int ti1570_scan_tx_dma_entry_sing
916     /* Generate an interrupt if required */     /* Generate an interrupt if required */
917     if (tde->ctrl_buf & TI1570_TX_DMA_TCR_SELECT)     if (tde->ctrl_buf & TI1570_TX_DMA_TCR_SELECT)
918     {     {
919        if (((d->iregs[TI1570_REG_STATUS] & TI1570_CFG_BP_SEL) && buf_end) ||        if (((d->iregs[TI1570_REG_CONFIG] & TI1570_CFG_BP_SEL) && buf_end) ||
920            pkt_end)            pkt_end)
921        {        {
922           d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_CP_TX;           d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_CP_TX;
923           pci_dev_trigger_irq(d->vm,d->pci_dev_ti);           dev_pa_a1_update_irq_status(d);
924        }        }
925     }     }
926    
# Line 1034  static void ti1570_update_rx_cring(struc Line 1053  static void ti1570_update_rx_cring(struc
1053    
1054        /* generate the appropriate IRQ */        /* generate the appropriate IRQ */
1055        d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_CP_RX;        d->iregs[TI1570_REG_STATUS] |= TI1570_STAT_CP_RX;
1056        pci_dev_trigger_irq(d->vm,d->pci_dev_ti);        dev_pa_a1_update_irq_status(d);
1057     } else  {     } else  {
1058        rcr_end = (d->iregs[TI1570_REG_RX_CRING_SIZE] >> 16);        rcr_end = (d->iregs[TI1570_REG_RX_CRING_SIZE] >> 16);
1059        rcr_end &= TI1570_RCR_SIZE_MASK;        rcr_end &= TI1570_RCR_SIZE_MASK;
# Line 1438  static int ti1570_handle_rx_cell(netio_d Line 1457  static int ti1570_handle_rx_cell(netio_d
1457  /*  /*
1458   * pci_ti1570_read()   * pci_ti1570_read()
1459   */   */
1460  static m_uint32_t pci_ti1570_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_ti1570_read(cpu_gen_t *cpu,struct pci_device *dev,
1461                                    int reg)                                    int reg)
1462  {  {
1463     struct pa_a1_data *d = dev->priv_data;     struct pa_a1_data *d = dev->priv_data;
# Line 1458  static m_uint32_t pci_ti1570_read(cpu_mi Line 1477  static m_uint32_t pci_ti1570_read(cpu_mi
1477  /*  /*
1478   * pci_ti1570_write()   * pci_ti1570_write()
1479   */   */
1480  static void pci_ti1570_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_ti1570_write(cpu_gen_t *cpu,struct pci_device *dev,
1481                               int reg,m_uint32_t value)                               int reg,m_uint32_t value)
1482  {  {
1483     struct pa_a1_data *d = dev->priv_data;     struct pa_a1_data *d = dev->priv_data;
# Line 1478  static void pci_ti1570_write(cpu_mips_t Line 1497  static void pci_ti1570_write(cpu_mips_t
1497  /*  /*
1498   * pci_plx9060es_read()   * pci_plx9060es_read()
1499   */   */
1500  static m_uint32_t pci_plx9060es_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_plx9060es_read(cpu_gen_t *cpu,struct pci_device *dev,
1501                                       int reg)                                       int reg)
1502  {  {
1503       struct pa_a1_data *d = dev->priv_data;
1504    
1505  #if DEBUG_ACCESS  #if DEBUG_ACCESS
1506     TI1570_LOG(d,"PLX9060ES","read reg 0x%x\n",reg);     TI1570_LOG(d,"PLX9060ES","read reg 0x%x\n",reg);
1507  #endif  #endif
# Line 1493  static m_uint32_t pci_plx9060es_read(cpu Line 1514  static m_uint32_t pci_plx9060es_read(cpu
1514  /*  /*
1515   * pci_plx9060es_write()   * pci_plx9060es_write()
1516   */   */
1517  static void pci_plx9060es_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_plx9060es_write(cpu_gen_t *cpu,struct pci_device *dev,
1518                                  int reg,m_uint32_t value)                                  int reg,m_uint32_t value)
1519  {  {
1520       struct pa_a1_data *d = dev->priv_data;
1521    
1522  #if DEBUG_ACCESS  #if DEBUG_ACCESS
1523     TI1570_LOG(d,"PLX9060ES","write reg 0x%x, value 0x%x\n",reg,value);     TI1570_LOG(d,"PLX9060ES","write reg 0x%x, value 0x%x\n",reg,value);
1524  #endif  #endif
# Line 1537  int dev_c7200_pa_a1_init(c7200_t *router Line 1560  int dev_c7200_pa_a1_init(c7200_t *router
1560     memset(d,0,sizeof(*d));     memset(d,0,sizeof(*d));
1561    
1562     /* Set the EEPROM */     /* Set the EEPROM */
1563     c7200_pa_set_eeprom(router,pa_bay,&eeprom_pa_a1);     c7200_pa_set_eeprom(router,pa_bay,cisco_eeprom_find_pa("PA-A1"));
1564    
1565     /* Add PCI device TI1570 */     /* Add PCI device TI1570 */
1566     pci_dev_ti = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,     pci_dev_ti = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,
1567                              TI1570_PCI_VENDOR_ID,TI1570_PCI_PRODUCT_ID,                              TI1570_PCI_VENDOR_ID,TI1570_PCI_PRODUCT_ID,
1568                              0,0,C7200_NETIO_IRQ,d,                              0,0,c7200_net_irq_for_slot_port(pa_bay,0),d,
1569                              NULL,pci_ti1570_read,pci_ti1570_write);                              NULL,pci_ti1570_read,pci_ti1570_write);
1570    
1571     if (!pci_dev_ti) {     if (!pci_dev_ti) {
# Line 1555  int dev_c7200_pa_a1_init(c7200_t *router Line 1578  int dev_c7200_pa_a1_init(c7200_t *router
1578     pci_dev_plx = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,     pci_dev_plx = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,
1579                               PLX_9060ES_PCI_VENDOR_ID,                               PLX_9060ES_PCI_VENDOR_ID,
1580                               PLX_9060ES_PCI_PRODUCT_ID,                               PLX_9060ES_PCI_PRODUCT_ID,
1581                               1,0,C7200_NETIO_IRQ,d,                               1,0,-1,d,
1582                               NULL,pci_plx9060es_read,pci_plx9060es_write);                               NULL,pci_plx9060es_read,pci_plx9060es_write);
1583    
1584     if (!pci_dev_plx) {     if (!pci_dev_plx) {
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