/[dynamips]/trunk/dev_c7200_mpfpga.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.5/dev_c7200_mpfpga.c revision 1 by dpavlin, Sat Oct 6 16:01:44 2007 UTC upstream/dynamips-0.2.7-RC1/dev_c7200_mpfpga.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco 7200 (Predator) simulation platform.   * Cisco router simulation platform.
3   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4   *   *
5   * Cisco C7200 (Predator) Midplane FPGA.   * Cisco c7200 Midplane FPGA.
6   */   */
7    
8  #include <stdio.h>  #include <stdio.h>
9  #include <stdlib.h>  #include <stdlib.h>
10  #include <string.h>  #include <string.h>
11    
12  #include "mips64.h"  #include "cpu.h"
13    #include "vm.h"
14  #include "dynamips.h"  #include "dynamips.h"
15  #include "memory.h"  #include "memory.h"
16  #include "device.h"  #include "device.h"
# Line 18  Line 19 
19    
20  #define DEBUG_UNKNOWN  1  #define DEBUG_UNKNOWN  1
21  #define DEBUG_ACCESS   0  #define DEBUG_ACCESS   0
22  #define DEBUG_OIR      0  #define DEBUG_OIR      1
23    
24  /*  /*
25   * Definitions for Port Adapter Status.   * Definitions for Port Adapter Status.
# Line 90  static const struct nmc93c46_eeprom_def Line 91  static const struct nmc93c46_eeprom_def
91     /* Bay 0 */     /* Bay 0 */
92     { BAY0_EEPROM_CLOCK_BIT , BAY0_EEPROM_SELECT_BIT,     { BAY0_EEPROM_CLOCK_BIT , BAY0_EEPROM_SELECT_BIT,
93       BAY0_EEPROM_DIN_BIT   , BAY0_EEPROM_DOUT_BIT,       BAY0_EEPROM_DIN_BIT   , BAY0_EEPROM_DOUT_BIT,
94       NULL, 0 },     },
95    
96     /* Bay 1 */     /* Bay 1 */
97     { BAY1_EEPROM_CLOCK_BIT , BAY1_EEPROM_SELECT_BIT,     { BAY1_EEPROM_CLOCK_BIT , BAY1_EEPROM_SELECT_BIT,
98       BAY1_EEPROM_DIN_BIT   , BAY1_EEPROM_DOUT_BIT,       BAY1_EEPROM_DIN_BIT   , BAY1_EEPROM_DOUT_BIT,
99       NULL, 0 },     },
100    
101     /* Bay 2 */     /* Bay 2 */
102     { BAY2_EEPROM_CLOCK_BIT , BAY2_EEPROM_SELECT_BIT,     { BAY2_EEPROM_CLOCK_BIT , BAY2_EEPROM_SELECT_BIT,
103       BAY2_EEPROM_DIN_BIT   , BAY2_EEPROM_DOUT_BIT,       BAY2_EEPROM_DIN_BIT   , BAY2_EEPROM_DOUT_BIT,
104       NULL, 0 },     },
105    
106     /* Bay 3 */     /* Bay 3 */
107     { BAY3_EEPROM_CLOCK_BIT , BAY3_EEPROM_SELECT_BIT,     { BAY3_EEPROM_CLOCK_BIT , BAY3_EEPROM_SELECT_BIT,
108       BAY3_EEPROM_DIN_BIT   , BAY3_EEPROM_DOUT_BIT,       BAY3_EEPROM_DIN_BIT   , BAY3_EEPROM_DOUT_BIT,
109       NULL, 0 },     },
110    
111     /* Bay 4 */     /* Bay 4 */
112     { BAY4_EEPROM_CLOCK_BIT , BAY4_EEPROM_SELECT_BIT,     { BAY4_EEPROM_CLOCK_BIT , BAY4_EEPROM_SELECT_BIT,
113       BAY4_EEPROM_DIN_BIT   , BAY4_EEPROM_DOUT_BIT,       BAY4_EEPROM_DIN_BIT   , BAY4_EEPROM_DOUT_BIT,
114       NULL, 0 },     },
115    
116     /* Bay 5 */     /* Bay 5 */
117     { BAY5_EEPROM_CLOCK_BIT , BAY5_EEPROM_SELECT_BIT,     { BAY5_EEPROM_CLOCK_BIT , BAY5_EEPROM_SELECT_BIT,
118       BAY5_EEPROM_DIN_BIT   , BAY5_EEPROM_DOUT_BIT,       BAY5_EEPROM_DIN_BIT   , BAY5_EEPROM_DOUT_BIT,
119       NULL, 0 },     },
120    
121     /* Bay 6 */     /* Bay 6 */
122     { BAY6_EEPROM_CLOCK_BIT , BAY6_EEPROM_SELECT_BIT,     { BAY6_EEPROM_CLOCK_BIT , BAY6_EEPROM_SELECT_BIT,
123       BAY6_EEPROM_DIN_BIT   , BAY6_EEPROM_DOUT_BIT,       BAY6_EEPROM_DIN_BIT   , BAY6_EEPROM_DOUT_BIT,
124       NULL, 0 },     },
125  };  };
126    
127  /* EEPROM group #1 (Bays 0, 1, 3, 4) */  /* EEPROM group #1 (Bays 0, 1, 3, 4) */
128  static const struct nmc93c46_group eeprom_bays_g1 = {  static const struct nmc93c46_group eeprom_bays_g1 = {
129     4, 0, "PA Bays (Group #1) EEPROM", FALSE,     4, 0, "PA Bays (Group #1) EEPROM", FALSE,
130    
131     { NULL, NULL, NULL, NULL },     { &eeprom_bay_def[0], &eeprom_bay_def[1],
132         &eeprom_bay_def[3], &eeprom_bay_def[4],
133     { { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0},     },
      { 0, 0, 0, 0, 0} },  
134  };  };
135    
136  /* EEPROM group #2 (Bays 2, 5, 6) */  /* EEPROM group #2 (Bays 2, 5, 6) */
137  static const struct nmc93c46_group eeprom_bays_g2 = {  static const struct nmc93c46_group eeprom_bays_g2 = {
138     3, 0, "PA Bays (Group #2) EEPROM", FALSE,     3, 0, "PA Bays (Group #2) EEPROM", FALSE,
   
    { NULL, NULL, NULL },  
139    
140     { { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0} },     { &eeprom_bay_def[2], &eeprom_bay_def[5], &eeprom_bay_def[6] },
141  };  };
142    
143  /* Midplane FPGA private data */  /* Midplane FPGA private data */
# Line 159  static void pa_update_status_reg(struct Line 157  static void pa_update_status_reg(struct
157    
158     /* PA Power. Bay 0 is always powered */     /* PA Power. Bay 0 is always powered */
159     res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK;     res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK;
160      
161     /* We fake power on bays defined by the final user */     /* We fake power on bays defined by the final user */
162     if (c7200_pa_check_eeprom(d->router,1))     if (c7200_pa_check_eeprom(d->router,1))
163        res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK;        res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK;
# Line 185  static void pa_update_status_reg(struct Line 183  static void pa_update_status_reg(struct
183  /*  /*
184   * dev_mpfpga_access()   * dev_mpfpga_access()
185   */   */
186  void *dev_c7200_mpfpga_access(cpu_mips_t *cpu,struct vdevice *dev,  void *dev_c7200_mpfpga_access(cpu_gen_t *cpu,struct vdevice *dev,
187                                m_uint32_t offset,u_int op_size,u_int op_type,                                m_uint32_t offset,u_int op_size,u_int op_type,
188                                m_uint64_t *data)                                m_uint64_t *data)
189  {  {
# Line 201  void *dev_c7200_mpfpga_access(cpu_mips_t Line 199  void *dev_c7200_mpfpga_access(cpu_mips_t
199  #if DEBUG_ACCESS  #if DEBUG_ACCESS
200     if (op_type == MTS_READ) {     if (op_type == MTS_READ) {
201        cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",        cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n",
202                offset,cpu->pc,op_size);                offset,cpu_get_pc(cpu),op_size);
203     } else {     } else {
204        cpu_log(cpu,"MP_FPGA",        cpu_log(cpu,"MP_FPGA",
205                "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",                "writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n",
206                offset,cpu->pc,*data,op_size);                offset,cpu_get_pc(cpu),*data,op_size);
207     }     }
208  #endif  #endif
209    
# Line 242  void *dev_c7200_mpfpga_access(cpu_mips_t Line 240  void *dev_c7200_mpfpga_access(cpu_mips_t
240           if (op_type == MTS_READ)           if (op_type == MTS_READ)
241              *data = 0x66666600 & d->pa_status_reg;              *data = 0x66666600 & d->pa_status_reg;
242    
243           mips64_clear_irq(cpu,C7200_PA_MGMT_IRQ);           vm_clear_irq(d->router->vm,C7200_PA_MGMT_IRQ);
244           break;           break;
245    
246        case 0x48:  /* ??? (test) */        case 0x48:  /* ??? (test) */
# Line 261  void *dev_c7200_mpfpga_access(cpu_mips_t Line 259  void *dev_c7200_mpfpga_access(cpu_mips_t
259           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
260  #if DEBUG_OIR  #if DEBUG_OIR
261              cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n",              cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n",
262                      offset,cpu->pc,d->router->oir_status);                      offset,cpu_get_pc(cpu),d->router->oir_status);
263  #endif  #endif
264              *data = d->router->oir_status;              *data = d->router->oir_status;
265                vm_clear_irq(d->router->vm,C7200_OIR_IRQ);
266           } else {           } else {
267  #if DEBUG_OIR  #if DEBUG_OIR
268              cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx "              cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx "
269                      "(data=0x%llx)\n",offset,cpu->pc,*data);                      "(data=0x%llx)\n",offset,cpu_get_pc(cpu),*data);
270  #endif  #endif
271              d->router->oir_status &= ~(*data);              d->router->oir_status &= ~(*data);
272              vm_clear_irq(d->router->vm,C7200_OIR_IRQ);                                  vm_clear_irq(d->router->vm,C7200_OIR_IRQ);                    
# Line 281  void *dev_c7200_mpfpga_access(cpu_mips_t Line 280  void *dev_c7200_mpfpga_access(cpu_mips_t
280        case 0x78:        case 0x78:
281           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
282  #if DEBUG_OIR  #if DEBUG_OIR
283              cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n",cpu->pc);              cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n",
284                        cpu_get_pc(cpu));
285  #endif  #endif
286              *data = 0x00;              *data = 0x00;
287           } else {           } else {
288  #if DEBUG_OIR  #if DEBUG_OIR
289              cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx "              cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx "
290                    "(data=0x%llx)\n",cpu->pc,*data);                    "(data=0x%llx)\n",cpu_get_pc(cpu),*data);
291  #endif  #endif
292           }           }
293           break;           break;
# Line 330  void *dev_c7200_mpfpga_access(cpu_mips_t Line 330  void *dev_c7200_mpfpga_access(cpu_mips_t
330        default:        default:
331           if (op_type == MTS_READ) {           if (op_type == MTS_READ) {
332              cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n",              cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n",
333                      offset,cpu->pc);                      offset,cpu_get_pc(cpu));
334           } else {           } else {
335              cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, "              cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, "
336                      "pc=0x%llx\n",offset,*data,cpu->pc);                      "pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
337           }           }
338  #endif  #endif
339     }     }
# Line 344  void *dev_c7200_mpfpga_access(cpu_mips_t Line 344  void *dev_c7200_mpfpga_access(cpu_mips_t
344  /* Initialize EEPROM groups */  /* Initialize EEPROM groups */
345  static void init_eeprom_groups(c7200_t *router)  static void init_eeprom_groups(c7200_t *router)
346  {  {
    struct nmc93c46_group *g;  
    int i;  
   
    for(i=0;i<C7200_MAX_PA_BAYS;i++) {  
       memcpy(&router->pa_bay[i].eeprom,&eeprom_bay_def[i],  
              sizeof(struct nmc93c46_eeprom_def));  
    }  
   
347     /* Group 1: bays 0, 1, 3, 4 */     /* Group 1: bays 0, 1, 3, 4 */
348     g = &router->pa_eeprom_g1;     router->pa_eeprom_g1 = eeprom_bays_g1;
349     memcpy(g,&eeprom_bays_g1,sizeof(struct nmc93c46_group));     router->pa_eeprom_g1.eeprom[0] = &router->pa_bay[0].eeprom;
350     g->def[0] = &router->pa_bay[0].eeprom;     router->pa_eeprom_g1.eeprom[1] = &router->pa_bay[1].eeprom;
351     g->def[1] = &router->pa_bay[1].eeprom;     router->pa_eeprom_g1.eeprom[2] = &router->pa_bay[3].eeprom;
352     g->def[2] = &router->pa_bay[3].eeprom;     router->pa_eeprom_g1.eeprom[3] = &router->pa_bay[4].eeprom;
    g->def[3] = &router->pa_bay[4].eeprom;  
353    
354     /* Group 2: bays 2, 5, 6 */     /* Group 2: bays 2, 5, 6 */
355     g = &router->pa_eeprom_g2;     router->pa_eeprom_g2 = eeprom_bays_g2;
356     memcpy(g,&eeprom_bays_g2,sizeof(struct nmc93c46_group));     router->pa_eeprom_g2.eeprom[0] = &router->pa_bay[2].eeprom;
357     g->def[0] = &router->pa_bay[2].eeprom;     router->pa_eeprom_g2.eeprom[1] = &router->pa_bay[5].eeprom;
358     g->def[1] = &router->pa_bay[5].eeprom;     router->pa_eeprom_g2.eeprom[2] = &router->pa_bay[6].eeprom;
    g->def[2] = &router->pa_bay[6].eeprom;  
   
    /* Set empty EEPROMs for all slots */  
    for(i=0;i<C7200_MAX_PA_BAYS;i++)  
       c7200_pa_unset_eeprom(router,i);  
359  }  }
360    
361  /* Shutdown the MP FPGA device */  /* Shutdown the MP FPGA device */
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