1 |
/* |
/* |
2 |
* Cisco 7200 (Predator) simulation platform. |
* Cisco router simulation platform. |
3 |
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
* Copyright (c) 2005-2007 Christophe Fillot (cf@utc.fr) |
4 |
* |
* |
5 |
* Cisco C7200 (Predator) Midplane FPGA. |
* Cisco c7200 Midplane FPGA. |
6 |
*/ |
*/ |
7 |
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|
8 |
#include <stdio.h> |
#include <stdio.h> |
9 |
#include <stdlib.h> |
#include <stdlib.h> |
10 |
#include <string.h> |
#include <string.h> |
11 |
|
|
12 |
#include "mips64.h" |
#include "cpu.h" |
13 |
|
#include "vm.h" |
14 |
#include "dynamips.h" |
#include "dynamips.h" |
15 |
#include "memory.h" |
#include "memory.h" |
16 |
#include "device.h" |
#include "device.h" |
17 |
#include "nmc93c46.h" |
#include "nmc93cX6.h" |
18 |
#include "dev_c7200.h" |
#include "dev_c7200.h" |
19 |
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|
20 |
#define DEBUG_UNKNOWN 1 |
#define DEBUG_UNKNOWN 1 |
21 |
#define DEBUG_ACCESS 0 |
#define DEBUG_ACCESS 0 |
22 |
#define DEBUG_OIR 0 |
#define DEBUG_NET_IRQ 0 |
23 |
|
#define DEBUG_OIR 1 |
24 |
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|
25 |
/* |
/* |
26 |
* Definitions for Port Adapter Status. |
* Definitions for Port Adapter Status. |
88 |
#define BAY6_EEPROM_DOUT_BIT 22 |
#define BAY6_EEPROM_DOUT_BIT 22 |
89 |
|
|
90 |
/* PA Bay EEPROM definitions */ |
/* PA Bay EEPROM definitions */ |
91 |
static const struct nmc93c46_eeprom_def eeprom_bay_def[C7200_MAX_PA_BAYS] = { |
static const struct nmc93cX6_eeprom_def eeprom_bay_def[C7200_MAX_PA_BAYS] = { |
92 |
/* Bay 0 */ |
/* Bay 0 */ |
93 |
{ BAY0_EEPROM_CLOCK_BIT , BAY0_EEPROM_SELECT_BIT, |
{ BAY0_EEPROM_CLOCK_BIT , BAY0_EEPROM_SELECT_BIT, |
94 |
BAY0_EEPROM_DIN_BIT , BAY0_EEPROM_DOUT_BIT, |
BAY0_EEPROM_DIN_BIT , BAY0_EEPROM_DOUT_BIT, |
95 |
NULL, 0 }, |
}, |
96 |
|
|
97 |
/* Bay 1 */ |
/* Bay 1 */ |
98 |
{ BAY1_EEPROM_CLOCK_BIT , BAY1_EEPROM_SELECT_BIT, |
{ BAY1_EEPROM_CLOCK_BIT , BAY1_EEPROM_SELECT_BIT, |
99 |
BAY1_EEPROM_DIN_BIT , BAY1_EEPROM_DOUT_BIT, |
BAY1_EEPROM_DIN_BIT , BAY1_EEPROM_DOUT_BIT, |
100 |
NULL, 0 }, |
}, |
101 |
|
|
102 |
/* Bay 2 */ |
/* Bay 2 */ |
103 |
{ BAY2_EEPROM_CLOCK_BIT , BAY2_EEPROM_SELECT_BIT, |
{ BAY2_EEPROM_CLOCK_BIT , BAY2_EEPROM_SELECT_BIT, |
104 |
BAY2_EEPROM_DIN_BIT , BAY2_EEPROM_DOUT_BIT, |
BAY2_EEPROM_DIN_BIT , BAY2_EEPROM_DOUT_BIT, |
105 |
NULL, 0 }, |
}, |
106 |
|
|
107 |
/* Bay 3 */ |
/* Bay 3 */ |
108 |
{ BAY3_EEPROM_CLOCK_BIT , BAY3_EEPROM_SELECT_BIT, |
{ BAY3_EEPROM_CLOCK_BIT , BAY3_EEPROM_SELECT_BIT, |
109 |
BAY3_EEPROM_DIN_BIT , BAY3_EEPROM_DOUT_BIT, |
BAY3_EEPROM_DIN_BIT , BAY3_EEPROM_DOUT_BIT, |
110 |
NULL, 0 }, |
}, |
111 |
|
|
112 |
/* Bay 4 */ |
/* Bay 4 */ |
113 |
{ BAY4_EEPROM_CLOCK_BIT , BAY4_EEPROM_SELECT_BIT, |
{ BAY4_EEPROM_CLOCK_BIT , BAY4_EEPROM_SELECT_BIT, |
114 |
BAY4_EEPROM_DIN_BIT , BAY4_EEPROM_DOUT_BIT, |
BAY4_EEPROM_DIN_BIT , BAY4_EEPROM_DOUT_BIT, |
115 |
NULL, 0 }, |
}, |
116 |
|
|
117 |
/* Bay 5 */ |
/* Bay 5 */ |
118 |
{ BAY5_EEPROM_CLOCK_BIT , BAY5_EEPROM_SELECT_BIT, |
{ BAY5_EEPROM_CLOCK_BIT , BAY5_EEPROM_SELECT_BIT, |
119 |
BAY5_EEPROM_DIN_BIT , BAY5_EEPROM_DOUT_BIT, |
BAY5_EEPROM_DIN_BIT , BAY5_EEPROM_DOUT_BIT, |
120 |
NULL, 0 }, |
}, |
121 |
|
|
122 |
/* Bay 6 */ |
/* Bay 6 */ |
123 |
{ BAY6_EEPROM_CLOCK_BIT , BAY6_EEPROM_SELECT_BIT, |
{ BAY6_EEPROM_CLOCK_BIT , BAY6_EEPROM_SELECT_BIT, |
124 |
BAY6_EEPROM_DIN_BIT , BAY6_EEPROM_DOUT_BIT, |
BAY6_EEPROM_DIN_BIT , BAY6_EEPROM_DOUT_BIT, |
125 |
NULL, 0 }, |
}, |
126 |
}; |
}; |
127 |
|
|
128 |
/* EEPROM group #1 (Bays 0, 1, 3, 4) */ |
/* EEPROM group #1 (Bays 0, 1, 3, 4) */ |
129 |
static const struct nmc93c46_group eeprom_bays_g1 = { |
static const struct nmc93cX6_group eeprom_bays_g1 = { |
130 |
4, 0, "PA Bays (Group #1) EEPROM", FALSE, |
EEPROM_TYPE_NMC93C46, 4, 0, "PA Bays (Group #1) EEPROM", FALSE, |
131 |
|
|
132 |
{ NULL, NULL, NULL, NULL }, |
{ &eeprom_bay_def[0], &eeprom_bay_def[1], |
133 |
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&eeprom_bay_def[3], &eeprom_bay_def[4], |
134 |
{ { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, |
}, |
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{ 0, 0, 0, 0, 0} }, |
|
135 |
}; |
}; |
136 |
|
|
137 |
/* EEPROM group #2 (Bays 2, 5, 6) */ |
/* EEPROM group #2 (Bays 2, 5, 6) */ |
138 |
static const struct nmc93c46_group eeprom_bays_g2 = { |
static const struct nmc93cX6_group eeprom_bays_g2 = { |
139 |
3, 0, "PA Bays (Group #2) EEPROM", FALSE, |
EEPROM_TYPE_NMC93C46, 3, 0, "PA Bays (Group #2) EEPROM", FALSE, |
140 |
|
|
141 |
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{ &eeprom_bay_def[2], &eeprom_bay_def[5], &eeprom_bay_def[6] }, |
142 |
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}; |
143 |
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|
144 |
{ NULL, NULL, NULL }, |
/* Network IRQ distribution */ |
145 |
|
struct net_irq_distrib { |
146 |
|
u_int reg; |
147 |
|
u_int offset; |
148 |
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}; |
149 |
|
|
150 |
{ { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0}, { 0, 0, 0, 0, 0} }, |
static struct net_irq_distrib net_irq_dist[C7200_MAX_PA_BAYS] = { |
151 |
|
{ 0, 0 }, /* Slot 0: reg 0x10, 0x000000XX */ |
152 |
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{ 0, 8 }, /* Slot 1: reg 0x10, 0x0000XX00 */ |
153 |
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{ 1, 8 }, /* Slot 2: reg 0x18, 0x0000XX00 */ |
154 |
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{ 0, 24 }, /* Slot 3: reg 0x10, 0xXX000000 */ |
155 |
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{ 0, 16 }, /* Slot 4: reg 0x10, 0x00XX0000 */ |
156 |
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{ 1, 24 }, /* Slot 5: reg 0x18, 0xXX000000 */ |
157 |
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{ 1, 16 }, /* Slot 6: reg 0x18, 0x00XX0000 */ |
158 |
}; |
}; |
159 |
|
|
160 |
/* Midplane FPGA private data */ |
/* Midplane FPGA private data */ |
161 |
struct mpfpga_data { |
struct c7200_mpfpga_data { |
162 |
vm_obj_t vm_obj; |
vm_obj_t vm_obj; |
163 |
struct vdevice dev; |
struct vdevice dev; |
164 |
|
|
165 |
c7200_t *router; |
c7200_t *router; |
166 |
m_uint32_t pa_status_reg; |
m_uint32_t pa_status_reg; |
167 |
m_uint32_t pa_ctrl_reg; |
m_uint32_t pa_ctrl_reg; |
168 |
|
|
169 |
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m_uint32_t net_irq_status[2]; |
170 |
|
m_uint32_t net_irq_mask[2]; |
171 |
}; |
}; |
172 |
|
|
173 |
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/* Update network interrupt status */ |
174 |
|
static inline void dev_c7200_mpfpga_net_update_irq(struct c7200_mpfpga_data *d) |
175 |
|
{ |
176 |
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int status; |
177 |
|
|
178 |
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status = (d->net_irq_status[0] & d->net_irq_mask[0]) || |
179 |
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(d->net_irq_status[1] & d->net_irq_mask[1]); |
180 |
|
|
181 |
|
if (status) { |
182 |
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vm_set_irq(d->router->vm,C7200_NETIO_IRQ); |
183 |
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} else { |
184 |
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vm_clear_irq(d->router->vm,C7200_NETIO_IRQ); |
185 |
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} |
186 |
|
} |
187 |
|
|
188 |
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/* Trigger a Network IRQ for the specified slot/port */ |
189 |
|
void dev_c7200_mpfpga_net_set_irq(struct c7200_mpfpga_data *d, |
190 |
|
u_int slot,u_int port) |
191 |
|
{ |
192 |
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struct net_irq_distrib *irq_dist; |
193 |
|
|
194 |
|
#if DEBUG_NET_IRQ |
195 |
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vm_log(d->router->vm,"MP_FPGA","setting NetIRQ for slot %u port %u\n", |
196 |
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slot,port); |
197 |
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#endif |
198 |
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irq_dist = &net_irq_dist[slot]; |
199 |
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d->net_irq_status[irq_dist->reg] |= 1 << (irq_dist->offset + port); |
200 |
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dev_c7200_mpfpga_net_update_irq(d); |
201 |
|
} |
202 |
|
|
203 |
|
/* Clear a Network IRQ for the specified slot/port */ |
204 |
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void dev_c7200_mpfpga_net_clear_irq(struct c7200_mpfpga_data *d, |
205 |
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u_int slot,u_int port) |
206 |
|
{ |
207 |
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struct net_irq_distrib *irq_dist; |
208 |
|
|
209 |
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#if DEBUG_NET_IRQ |
210 |
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vm_log(d->router->vm,"MP_FPGA","clearing NetIRQ for slot %u port %u\n", |
211 |
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slot,port); |
212 |
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#endif |
213 |
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irq_dist = &net_irq_dist[slot]; |
214 |
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d->net_irq_status[irq_dist->reg] &= ~(1 << (irq_dist->offset + port)); |
215 |
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dev_c7200_mpfpga_net_update_irq(d); |
216 |
|
} |
217 |
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|
218 |
/* Update Port Adapter Status */ |
/* Update Port Adapter Status */ |
219 |
static void pa_update_status_reg(struct mpfpga_data *d) |
static void pa_update_status_reg(struct c7200_mpfpga_data *d) |
220 |
{ |
{ |
221 |
m_uint32_t res = 0; |
m_uint32_t res = 0; |
222 |
|
|
223 |
/* PA Power. Bay 0 is always powered */ |
/* PA Power. Bay 0 is always powered */ |
224 |
res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK; |
res |= PCI_BAY0_5V_OK | PCI_BAY0_3V_OK; |
225 |
|
|
226 |
/* We fake power on bays defined by the final user */ |
/* We fake power on bays defined by the final user */ |
227 |
if (c7200_pa_check_eeprom(d->router,1)) |
if (c7200_pa_check_eeprom(d->router,1)) |
228 |
res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK; |
res |= PCI_BAY1_5V_OK | PCI_BAY1_3V_OK; |
248 |
/* |
/* |
249 |
* dev_mpfpga_access() |
* dev_mpfpga_access() |
250 |
*/ |
*/ |
251 |
void *dev_c7200_mpfpga_access(cpu_mips_t *cpu,struct vdevice *dev, |
void *dev_c7200_mpfpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
252 |
m_uint32_t offset,u_int op_size,u_int op_type, |
m_uint32_t offset,u_int op_size,u_int op_type, |
253 |
m_uint64_t *data) |
m_uint64_t *data) |
254 |
{ |
{ |
255 |
struct mpfpga_data *d = dev->priv_data; |
struct c7200_mpfpga_data *d = dev->priv_data; |
256 |
|
|
257 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
258 |
*data = 0x0; |
*data = 0x0; |
264 |
#if DEBUG_ACCESS |
#if DEBUG_ACCESS |
265 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
266 |
cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
267 |
offset,cpu->pc,op_size); |
offset,cpu_get_pc(cpu),op_size); |
268 |
} else { |
} else { |
269 |
cpu_log(cpu,"MP_FPGA", |
cpu_log(cpu,"MP_FPGA", |
270 |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
271 |
offset,cpu->pc,*data,op_size); |
offset,cpu_get_pc(cpu),*data,op_size); |
272 |
} |
} |
273 |
#endif |
#endif |
274 |
|
|
275 |
switch(offset) { |
switch(offset) { |
276 |
case 0x10: /* interrupt mask, should be done more efficiently */ |
/* Interrupt status for slots 0, 1, 3, 4 */ |
277 |
|
case 0x10: |
278 |
case 0x11: |
case 0x11: |
279 |
case 0x12: |
case 0x12: |
280 |
case 0x13: |
case 0x13: |
281 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) |
282 |
*data = 0xFFFFFFFF; |
*data = d->net_irq_status[0]; |
|
vm_clear_irq(d->router->vm,C7200_NETIO_IRQ); |
|
|
} |
|
283 |
break; |
break; |
284 |
|
|
285 |
case 0x18: /* interrupt mask, should be done more efficiently */ |
/* Interrupt status for slots 2, 5, 6 */ |
286 |
|
case 0x18: |
287 |
case 0x19: |
case 0x19: |
288 |
case 0x1a: |
case 0x1a: |
289 |
|
case 0x1b: |
290 |
|
if (op_type == MTS_READ) |
291 |
|
*data = d->net_irq_status[1]; |
292 |
|
break; |
293 |
|
|
294 |
|
/* Interrupt mask for slots 0, 1, 3, 4 */ |
295 |
|
case 0x20: |
296 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
297 |
*data = 0xFFFFFFFF; |
*data = d->net_irq_mask[0]; |
298 |
vm_clear_irq(d->router->vm,C7200_NETIO_IRQ); |
} else { |
299 |
|
d->net_irq_mask[0] = *data; |
300 |
|
dev_c7200_mpfpga_net_update_irq(d); |
301 |
|
} |
302 |
|
break; |
303 |
|
|
304 |
|
/* Interrupt mask for slots 2, 5, 6 */ |
305 |
|
case 0x28: |
306 |
|
if (op_type == MTS_READ) { |
307 |
|
*data = d->net_irq_mask[1]; |
308 |
|
} else { |
309 |
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d->net_irq_mask[1] = *data; |
310 |
|
dev_c7200_mpfpga_net_update_irq(d); |
311 |
} |
} |
312 |
break; |
break; |
313 |
|
|
324 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) |
325 |
*data = 0x66666600 & d->pa_status_reg; |
*data = 0x66666600 & d->pa_status_reg; |
326 |
|
|
327 |
mips64_clear_irq(cpu,C7200_PA_MGMT_IRQ); |
vm_clear_irq(d->router->vm,C7200_PA_MGMT_IRQ); |
328 |
break; |
break; |
329 |
|
|
330 |
case 0x48: /* ??? (test) */ |
case 0x48: /* ??? (test) */ |
343 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
344 |
#if DEBUG_OIR |
#if DEBUG_OIR |
345 |
cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n", |
cpu_log(cpu,"MP_FPGA","reading reg 0x%x at pc=0x%llx, val=0x%x\n", |
346 |
offset,cpu->pc,d->router->oir_status); |
offset,cpu_get_pc(cpu),d->router->oir_status); |
347 |
#endif |
#endif |
348 |
*data = d->router->oir_status; |
*data = d->router->oir_status; |
349 |
|
vm_clear_irq(d->router->vm,C7200_OIR_IRQ); |
350 |
} else { |
} else { |
351 |
#if DEBUG_OIR |
#if DEBUG_OIR |
352 |
cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx " |
cpu_log(cpu,"MP_FPGA","writing reg 0x%x at pc=0x%llx " |
353 |
"(data=0x%llx)\n",offset,cpu->pc,*data); |
"(data=0x%llx)\n",offset,cpu_get_pc(cpu),*data); |
354 |
#endif |
#endif |
355 |
d->router->oir_status &= ~(*data); |
d->router->oir_status &= ~(*data); |
356 |
vm_clear_irq(d->router->vm,C7200_OIR_IRQ); |
vm_clear_irq(d->router->vm,C7200_OIR_IRQ); |
364 |
case 0x78: |
case 0x78: |
365 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
366 |
#if DEBUG_OIR |
#if DEBUG_OIR |
367 |
cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n",cpu->pc); |
cpu_log(cpu,"MP_FPGA","reading 0x78 at pc=0x%llx\n", |
368 |
|
cpu_get_pc(cpu)); |
369 |
#endif |
#endif |
370 |
*data = 0x00; |
*data = 0x00; |
371 |
} else { |
} else { |
372 |
#if DEBUG_OIR |
#if DEBUG_OIR |
373 |
cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx " |
cpu_log(cpu,"MP_FPGA","writing reg 0x78 at pc=0x%llx " |
374 |
"(data=0x%llx)\n",cpu->pc,*data); |
"(data=0x%llx)\n",cpu_get_pc(cpu),*data); |
375 |
#endif |
#endif |
376 |
} |
} |
377 |
break; |
break; |
395 |
|
|
396 |
case 0x60: /* EEPROM for PA in slots 0,1,3,4 */ |
case 0x60: /* EEPROM for PA in slots 0,1,3,4 */ |
397 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
398 |
nmc93c46_write(&d->router->pa_eeprom_g1,*data); |
nmc93cX6_write(&d->router->pa_eeprom_g1,*data); |
399 |
else |
else |
400 |
*data = nmc93c46_read(&d->router->pa_eeprom_g1); |
*data = nmc93cX6_read(&d->router->pa_eeprom_g1); |
401 |
break; |
break; |
402 |
|
|
403 |
case 0x68: /* EEPROM for PA in slots 2,5,6 */ |
case 0x68: /* EEPROM for PA in slots 2,5,6 */ |
404 |
if (op_type == MTS_WRITE) |
if (op_type == MTS_WRITE) |
405 |
nmc93c46_write(&d->router->pa_eeprom_g2,*data); |
nmc93cX6_write(&d->router->pa_eeprom_g2,*data); |
406 |
else |
else |
407 |
*data = nmc93c46_read(&d->router->pa_eeprom_g2); |
*data = nmc93cX6_read(&d->router->pa_eeprom_g2); |
408 |
break; |
break; |
409 |
|
|
410 |
case 0x7b: /* ??? */ |
case 0x7b: /* ??? */ |
414 |
default: |
default: |
415 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
416 |
cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n", |
cpu_log(cpu,"MP_FPGA","read from addr 0x%x, pc=0x%llx\n", |
417 |
offset,cpu->pc); |
offset,cpu_get_pc(cpu)); |
418 |
} else { |
} else { |
419 |
cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, " |
cpu_log(cpu,"MP_FPGA","write to addr 0x%x, value=0x%llx, " |
420 |
"pc=0x%llx\n",offset,*data,cpu->pc); |
"pc=0x%llx\n",offset,*data,cpu_get_pc(cpu)); |
421 |
} |
} |
422 |
#endif |
#endif |
423 |
} |
} |
428 |
/* Initialize EEPROM groups */ |
/* Initialize EEPROM groups */ |
429 |
static void init_eeprom_groups(c7200_t *router) |
static void init_eeprom_groups(c7200_t *router) |
430 |
{ |
{ |
|
struct nmc93c46_group *g; |
|
|
int i; |
|
|
|
|
|
for(i=0;i<C7200_MAX_PA_BAYS;i++) { |
|
|
memcpy(&router->pa_bay[i].eeprom,&eeprom_bay_def[i], |
|
|
sizeof(struct nmc93c46_eeprom_def)); |
|
|
} |
|
|
|
|
431 |
/* Group 1: bays 0, 1, 3, 4 */ |
/* Group 1: bays 0, 1, 3, 4 */ |
432 |
g = &router->pa_eeprom_g1; |
router->pa_eeprom_g1 = eeprom_bays_g1; |
433 |
memcpy(g,&eeprom_bays_g1,sizeof(struct nmc93c46_group)); |
router->pa_eeprom_g1.eeprom[0] = &router->pa_bay[0].eeprom; |
434 |
g->def[0] = &router->pa_bay[0].eeprom; |
router->pa_eeprom_g1.eeprom[1] = &router->pa_bay[1].eeprom; |
435 |
g->def[1] = &router->pa_bay[1].eeprom; |
router->pa_eeprom_g1.eeprom[2] = &router->pa_bay[3].eeprom; |
436 |
g->def[2] = &router->pa_bay[3].eeprom; |
router->pa_eeprom_g1.eeprom[3] = &router->pa_bay[4].eeprom; |
|
g->def[3] = &router->pa_bay[4].eeprom; |
|
437 |
|
|
438 |
/* Group 2: bays 2, 5, 6 */ |
/* Group 2: bays 2, 5, 6 */ |
439 |
g = &router->pa_eeprom_g2; |
router->pa_eeprom_g2 = eeprom_bays_g2; |
440 |
memcpy(g,&eeprom_bays_g2,sizeof(struct nmc93c46_group)); |
router->pa_eeprom_g2.eeprom[0] = &router->pa_bay[2].eeprom; |
441 |
g->def[0] = &router->pa_bay[2].eeprom; |
router->pa_eeprom_g2.eeprom[1] = &router->pa_bay[5].eeprom; |
442 |
g->def[1] = &router->pa_bay[5].eeprom; |
router->pa_eeprom_g2.eeprom[2] = &router->pa_bay[6].eeprom; |
|
g->def[2] = &router->pa_bay[6].eeprom; |
|
|
|
|
|
/* Set empty EEPROMs for all slots */ |
|
|
for(i=0;i<C7200_MAX_PA_BAYS;i++) |
|
|
c7200_pa_unset_eeprom(router,i); |
|
443 |
} |
} |
444 |
|
|
445 |
/* Shutdown the MP FPGA device */ |
/* Shutdown the MP FPGA device */ |
446 |
void dev_c7200_mpfpga_shutdown(vm_instance_t *vm,struct mpfpga_data *d) |
static void |
447 |
|
dev_c7200_mpfpga_shutdown(vm_instance_t *vm,struct c7200_mpfpga_data *d) |
448 |
{ |
{ |
449 |
if (d != NULL) { |
if (d != NULL) { |
450 |
/* Remove the device */ |
/* Remove the device */ |
455 |
} |
} |
456 |
} |
} |
457 |
|
|
458 |
/* |
/* Create the c7200 Midplane FPGA */ |
|
* dev_c7200_mpfpga_init() |
|
|
*/ |
|
459 |
int dev_c7200_mpfpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len) |
int dev_c7200_mpfpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len) |
460 |
{ |
{ |
461 |
struct mpfpga_data *d; |
struct c7200_mpfpga_data *d; |
462 |
|
|
463 |
/* Allocate private data structure */ |
/* Allocate private data structure */ |
464 |
if (!(d = malloc(sizeof(*d)))) { |
if (!(d = malloc(sizeof(*d)))) { |