/[dynamips]/trunk/dev_c7200_iofpga.c
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Contents of /trunk/dev_c7200_iofpga.c

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Revision 12 - (show annotations)
Sat Oct 6 16:45:40 2007 UTC (11 years, 7 months ago) by dpavlin
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1 /*
2 * Cisco router simulation platform.
3 * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4 *
5 * Cisco 7200 I/O FPGA:
6 * - Simulates a NMC93C46 Serial EEPROM as CPU and Midplane EEPROM.
7 * - Simulates a DALLAS DS1620 for Temperature Sensors.
8 * - Simulates voltage sensors.
9 * - Simulates console and AUX ports (SCN2681).
10 */
11
12 #include <stdio.h>
13 #include <stdlib.h>
14 #include <string.h>
15 #include <unistd.h>
16 #include <sys/types.h>
17
18 #include <termios.h>
19 #include <fcntl.h>
20 #include <pthread.h>
21
22 #include "ptask.h"
23 #include "cpu.h"
24 #include "vm.h"
25 #include "dynamips.h"
26 #include "memory.h"
27 #include "device.h"
28 #include "dev_vtty.h"
29 #include "nmc93cX6.h"
30 #include "ds1620.h"
31 #include "dev_c7200.h"
32
33 /* Debugging flags */
34 #define DEBUG_UNKNOWN 1
35 #define DEBUG_ACCESS 0
36 #define DEBUG_LED 0
37 #define DEBUG_IO_CTL 0
38 #define DEBUG_ENVM 0
39
40 /* DUART RX/TX status (SRA/SRB) */
41 #define DUART_RX_READY 0x01
42 #define DUART_TX_READY 0x04
43
44 /* DUART RX/TX Interrupt Status/Mask */
45 #define DUART_TXRDYA 0x01
46 #define DUART_RXRDYA 0x02
47 #define DUART_TXRDYB 0x10
48 #define DUART_RXRDYB 0x20
49
50 /* Definitions for CPU and Midplane Serial EEPROMs */
51 #define DO2_DATA_OUT_MIDPLANE 7
52 #define DO1_DATA_OUT_CPU 6
53 #define CS2_CHIP_SEL_MIDPLANE 5
54 #define SK2_CLOCK_MIDPLANE 4
55 #define DI2_DATA_IN_MIDPLANE 3
56 #define CS1_CHIP_SEL_CPU 2
57 #define SK1_CLOCK_CPU 1
58 #define DI1_DATA_IN_CPU 0
59
60 /* Definitions for PEM (NPE-B) Serial EEPROM */
61 #define DO1_DATA_OUT_PEM 3
62 #define DI1_DATA_IN_PEM 2
63 #define CS1_CHIP_SEL_PEM 1
64 #define SK1_CLOCK_PEM 0
65
66 /* Pack the NVRAM */
67 #define NVRAM_PACKED 0x04
68
69 /* 4 temperature sensors in a C7200 */
70 #define C7200_TEMP_SENSORS 4
71 #define C7200_DEFAULT_TEMP 22 /* default temperature: 22°C */
72
73 /* Voltages */
74 #define C7200_A2D_SAMPLES 9
75
76 /*
77 * A2D MUX Select definitions.
78 */
79 #define C7200_MUX_PS0 0x00 /* Power Supply 0 */
80 #define C7200_MUX_PS1 0x02 /* Power Supply 1 */
81 #define C7200_MUX_P3V 0x04 /* +3V */
82 #define C7200_MUX_P12V 0x08 /* +12V */
83 #define C7200_MUX_P5V 0x0a /* +5V */
84 #define C7200_MUX_N12V 0x0c /* -12V */
85
86 /* Analog To Digital Converters samples */
87 #define C7200_A2D_PS0 1150
88 #define C7200_A2D_PS1 1150
89
90 /* Voltage Samples */
91 #define C7200_A2D_P3V 1150
92 #define C7200_A2D_P12V 1150
93 #define C7200_A2D_P5V 1150
94 #define C7200_A2D_N12V 1150
95
96 /* IO FPGA structure */
97 struct iofpga_data {
98 vm_obj_t vm_obj;
99 struct vdevice dev;
100 c7200_t *router;
101
102 /* Lock test */
103 pthread_mutex_t lock;
104
105 /* Periodic task to trigger dummy DUART IRQ */
106 ptask_id_t duart_irq_tid;
107
108 /* DUART & Console Management */
109 u_int duart_isr,duart_imr,duart_irq_seq;
110
111 /* IO control register */
112 u_int io_ctrl_reg;
113
114 /* Temperature Control */
115 u_int temp_cfg_reg[C7200_TEMP_SENSORS];
116 u_int temp_deg_reg[C7200_TEMP_SENSORS];
117 u_int temp_clk_low;
118
119 u_int temp_cmd;
120 u_int temp_cmd_pos;
121
122 u_int temp_data;
123 u_int temp_data_pos;
124
125 /* Voltages */
126 u_int mux;
127
128 /* NPE-G2 environmental part */
129 m_uint32_t envm_r0,envm_r1,envm_r2;
130 };
131
132 #define IOFPGA_LOCK(d) pthread_mutex_lock(&(d)->lock)
133 #define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock)
134
135 /* CPU EEPROM definition */
136 static const struct nmc93cX6_eeprom_def eeprom_cpu_def = {
137 SK1_CLOCK_CPU, CS1_CHIP_SEL_CPU,
138 DI1_DATA_IN_CPU, DO1_DATA_OUT_CPU,
139 };
140
141 /* Midplane EEPROM definition */
142 static const struct nmc93cX6_eeprom_def eeprom_midplane_def = {
143 SK2_CLOCK_MIDPLANE, CS2_CHIP_SEL_MIDPLANE,
144 DI2_DATA_IN_MIDPLANE, DO2_DATA_OUT_MIDPLANE,
145 };
146
147 /* PEM (NPE-B) EEPROM definition */
148 static const struct nmc93cX6_eeprom_def eeprom_pem_def = {
149 SK1_CLOCK_PEM, CS1_CHIP_SEL_PEM, DI1_DATA_IN_PEM, DO1_DATA_OUT_PEM,
150 };
151
152 /* IOFPGA manages simultaneously CPU and Midplane EEPROM */
153 static const struct nmc93cX6_group eeprom_cpu_midplane = {
154 EEPROM_TYPE_NMC93C46, 2, 0,
155 EEPROM_DORD_NORMAL,
156 EEPROM_DOUT_HIGH,
157 EEPROM_DEBUG_DISABLED,
158 "CPU and Midplane EEPROM",
159 { &eeprom_cpu_def, &eeprom_midplane_def },
160 };
161
162 /*
163 * IOFPGA manages also PEM EEPROM (for NPE-B)
164 * PEM stands for "Power Entry Module":
165 * http://www.cisco.com/en/US/products/hw/routers/ps341/products_field_notice09186a00801cb26d.shtml
166 */
167 static const struct nmc93cX6_group eeprom_pem_npeb = {
168 EEPROM_TYPE_NMC93C46, 1, 0,
169 EEPROM_DORD_NORMAL,
170 EEPROM_DOUT_HIGH,
171 EEPROM_DEBUG_DISABLED,
172 "PEM (NPE-B) EEPROM",
173 { &eeprom_pem_def },
174 };
175
176 /* Reset DS1620 */
177 static void temp_reset(struct iofpga_data *d)
178 {
179 d->temp_cmd_pos = 0;
180 d->temp_cmd = 0;
181
182 d->temp_data_pos = 0;
183 d->temp_data = 0;
184 }
185
186 /* Write the temperature control data */
187 static void temp_write_ctrl(struct iofpga_data *d,u_char val)
188 {
189 switch(val) {
190 case DS1620_RESET_ON:
191 temp_reset(d);
192 break;
193
194 case DS1620_CLK_LOW:
195 d->temp_clk_low = 1;
196 break;
197
198 case DS1620_CLK_HIGH:
199 d->temp_clk_low = 0;
200 break;
201 }
202 }
203
204 /* Read a temperature control data */
205 static u_int temp_read_data(struct iofpga_data *d)
206 {
207 u_int i,data = 0;
208
209 switch(d->temp_cmd) {
210 case DS1620_READ_CONFIG:
211 for(i=0;i<C7200_TEMP_SENSORS;i++)
212 data |= ((d->temp_cfg_reg[i] >> d->temp_data_pos) & 1) << i;
213
214 d->temp_data_pos++;
215
216 if (d->temp_data_pos == DS1620_CONFIG_READ_SIZE)
217 temp_reset(d);
218
219 break;
220
221 case DS1620_READ_TEMP:
222 for(i=0;i<C7200_TEMP_SENSORS;i++)
223 data |= ((d->temp_deg_reg[i] >> d->temp_data_pos) & 1) << i;
224
225 d->temp_data_pos++;
226
227 if (d->temp_data_pos == DS1620_DATA_READ_SIZE)
228 temp_reset(d);
229
230 break;
231
232 default:
233 vm_log(d->router->vm,"IO_FPGA","temp_sensors: CMD = 0x%x\n",
234 d->temp_cmd);
235 }
236
237 return(data);
238 }
239
240 /* Write the temperature data write register */
241 static void temp_write_data(struct iofpga_data *d,u_char val)
242 {
243 if (val == DS1620_ENABLE_READ) {
244 d->temp_data_pos = 0;
245 return;
246 }
247
248 if (!d->temp_clk_low)
249 return;
250
251 /* Write a command */
252 if (d->temp_cmd_pos < DS1620_WRITE_SIZE)
253 {
254 if (val == DS1620_DATA_HIGH)
255 d->temp_cmd |= 1 << d->temp_cmd_pos;
256
257 d->temp_cmd_pos++;
258
259 if (d->temp_cmd_pos == DS1620_WRITE_SIZE) {
260 switch(d->temp_cmd) {
261 case DS1620_START_CONVT:
262 //printf("temp_sensors: IOS enabled continuous monitoring.\n");
263 temp_reset(d);
264 break;
265 case DS1620_READ_CONFIG:
266 case DS1620_READ_TEMP:
267 break;
268 default:
269 vm_log(d->router->vm,"IO_FPGA",
270 "temp_sensors: IOS sent command 0x%x.\n",
271 d->temp_cmd);
272 }
273 }
274 }
275 else
276 {
277 if (val == DS1620_DATA_HIGH)
278 d->temp_data |= 1 << d->temp_data_pos;
279
280 d->temp_data_pos++;
281 }
282 }
283
284 /* NPE-G2 environmental monitor reading */
285 static m_uint32_t g2_envm_read(struct iofpga_data *d)
286 {
287 m_uint32_t val = 0;
288 m_uint32_t p1;
289
290 p1 = ((d->envm_r2 & 0xFF) << 8) | d->envm_r0 >> 3;
291
292 switch(p1) {
293 case 0x2a00: /* CPU Die Temperature */
294 val = 0x3000;
295 break;
296 case 0x4c00: /* +3.30V */
297 val = 0x2a9;
298 break;
299 case 0x4c01: /* +1.50V */
300 val = 0x135;
301 break;
302 case 0x4c02: /* +2.50V */
303 val = 0x204;
304 break;
305 case 0x4c03: /* +1.80V */
306 val = 0x173;
307 break;
308 case 0x4c04: /* +1.20V */
309 val = 0xF7;
310 break;
311 case 0x4c05: /* VDD_CPU */
312 val = 0x108;
313 break;
314 case 0x4800: /* VDD_MEM */
315 val = 0x204;
316 break;
317 case 0x4801: /* VTT */
318 val = 0xF9;
319 break;
320 case 0x4802: /* +3.45V */
321 val = 0x2c8;
322 break;
323 case 0x4803: /* -11.95V*/
324 val = 0x260;
325 break;
326 case 0x4804: /* ? */
327 val = 0x111;
328 break;
329 case 0x4805: /* ? */
330 val = 0x111;
331 break;
332 case 0x4806: /* +5.15V */
333 val = 0x3F8;
334 break;
335 case 0x4807: /* +12.15V */
336 val = 0x33D;
337 break;
338 #if DEBUG_UNKNOWN
339 default:
340 vm_log(d->router->vm,"IO_FPGA","p1 = 0x%8.8x\n",p1);
341 #endif
342 }
343
344 return(htonl(val));
345 }
346
347 /* Console port input */
348 static void tty_con_input(vtty_t *vtty)
349 {
350 struct iofpga_data *d = vtty->priv_data;
351
352 IOFPGA_LOCK(d);
353 if (d->duart_imr & DUART_RXRDYA) {
354 d->duart_isr |= DUART_RXRDYA;
355 vm_set_irq(d->router->vm,C7200_DUART_IRQ);
356 }
357 IOFPGA_UNLOCK(d);
358 }
359
360 /* AUX port input */
361 static void tty_aux_input(vtty_t *vtty)
362 {
363 struct iofpga_data *d = vtty->priv_data;
364
365 IOFPGA_LOCK(d);
366 if (d->duart_imr & DUART_RXRDYB) {
367 d->duart_isr |= DUART_RXRDYB;
368 vm_set_irq(d->router->vm,C7200_DUART_IRQ);
369 }
370 IOFPGA_UNLOCK(d);
371 }
372
373 /* IRQ trickery for Console and AUX ports */
374 static int tty_trigger_dummy_irq(struct iofpga_data *d,void *arg)
375 {
376 u_int mask;
377
378 IOFPGA_LOCK(d);
379 d->duart_irq_seq++;
380
381 if (d->duart_irq_seq == 2) {
382 mask = DUART_TXRDYA|DUART_TXRDYB;
383 if (d->duart_imr & mask) {
384 d->duart_isr |= DUART_TXRDYA|DUART_TXRDYB;
385 vm_set_irq(d->router->vm,C7200_DUART_IRQ);
386 }
387
388 d->duart_irq_seq = 0;
389 }
390
391 IOFPGA_UNLOCK(d);
392 return(0);
393 }
394
395 /*
396 * dev_c7200_iofpga_access()
397 */
398 void *dev_c7200_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
399 m_uint32_t offset,u_int op_size,u_int op_type,
400 m_uint64_t *data)
401 {
402 struct iofpga_data *d = dev->priv_data;
403 vm_instance_t *vm = d->router->vm;
404 u_char odata;
405
406 if (op_type == MTS_READ)
407 *data = 0x0;
408
409 #if DEBUG_ACCESS
410 if (op_type == MTS_READ) {
411 cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx\n",
412 offset,cpu_get_pc(cpu));
413 } else {
414 cpu_log(cpu,"IO_FPGA","writing reg 0x%x at pc=0x%llx, data=0x%llx\n",
415 offset,cpu_get_pc(cpu),*data);
416 }
417 #endif
418
419 IOFPGA_LOCK(d);
420
421 switch(offset) {
422 case 0x294:
423 /*
424 * Unknown, seen in 12.4(6)T, and seems to be read at each
425 * network interrupt.
426 */
427 if (op_type == MTS_READ)
428 *data = 0x0;
429 break;
430
431 /* NPE-G1 test - unknown (value written: 0x01) */
432 case 0x338:
433 break;
434
435 /*
436 * NPE-G1/NPE-G2 - has influence on slot 0 / flash / pcmcia ...
437 * Bit 24: 1=I/O slot present
438 * Lower 16 bits: FPGA version (displayed by "sh c7200")
439 */
440 case 0x390:
441 if (op_type == MTS_READ) {
442 *data = 0x0102;
443
444 /* If we have an I/O slot, we use the I/O slot DUART */
445 if (vm_slot_check_eeprom(d->router->vm,0,0))
446 *data |= 0x01000000;
447 }
448 break;
449
450 /* I/O control register */
451 case 0x204:
452 if (op_type == MTS_WRITE) {
453 #if DEBUG_IO_CTL
454 vm_log(vm,"IO_FPGA","setting value 0x%llx in io_ctrl_reg\n",*data);
455 #endif
456 d->io_ctrl_reg = *data;
457 } else {
458 *data = d->io_ctrl_reg;
459 *data |= NVRAM_PACKED; /* Packed NVRAM */
460 }
461 break;
462
463 /* CPU/Midplane EEPROMs */
464 case 0x21c:
465 if (op_type == MTS_WRITE)
466 nmc93cX6_write(&d->router->sys_eeprom_g1,(u_int)(*data));
467 else
468 *data = nmc93cX6_read(&d->router->sys_eeprom_g1);
469 break;
470
471 /* PEM (NPE-B) EEPROM */
472 case 0x388:
473 if (op_type == MTS_WRITE)
474 nmc93cX6_write(&d->router->sys_eeprom_g2,(u_int)(*data));
475 else
476 *data = nmc93cX6_read(&d->router->sys_eeprom_g2);
477 break;
478
479 /* Watchdog */
480 case 0x234:
481 break;
482
483 /*
484 * FPGA release/presence ? Flash SIMM size:
485 * 0x0001: 2048K Flash (2 banks)
486 * 0x0504: 8192K Flash (2 banks)
487 * 0x0704: 16384K Flash (2 banks)
488 * 0x0904: 32768K Flash (2 banks)
489 * 0x0B04: 65536K Flash (2 banks)
490 * 0x2001: 1024K Flash (1 bank)
491 * 0x2504: 4096K Flash (1 bank)
492 * 0x2704: 8192K Flash (1 bank)
493 * 0x2904: 16384K Flash (1 bank)
494 * 0x2B04: 32768K Flash (1 bank)
495 *
496 * Number of Flash SIMM banks + size.
497 * Touching some lower bits causes problems with environmental monitor.
498 *
499 * It is displayed by command "sh bootflash: chips"
500 */
501 case 0x23c:
502 if (op_type == MTS_READ)
503 *data = 0x2704;
504 break;
505
506 /* LEDs */
507 case 0x244:
508 #if DEBUG_LED
509 vm_log(vm,"IO_FPGA","LED register is now 0x%x (0x%x)\n",
510 *data,(~*data) & 0x0F);
511 #endif
512 break;
513
514 /* ==== DUART SCN2681 (console/aux) ==== */
515 case 0x404: /* Mode Register A (MRA) */
516 break;
517
518 case 0x40c: /* Status Register A (SRA) */
519 if (op_type == MTS_READ) {
520 odata = 0;
521
522 if (vtty_is_char_avail(vm->vtty_con))
523 odata |= DUART_RX_READY;
524
525 odata |= DUART_TX_READY;
526
527 vm_clear_irq(vm,C7200_DUART_IRQ);
528 *data = odata;
529 }
530 break;
531
532 case 0x414: /* Command Register A (CRA) */
533 /* Disable TX = High */
534 if ((op_type == MTS_WRITE) && (*data & 0x8)) {
535 vm->vtty_con->managed_flush = TRUE;
536 vtty_flush(vm->vtty_con);
537 }
538 break;
539
540 case 0x41c: /* RX/TX Holding Register A (RHRA/THRA) */
541 if (op_type == MTS_WRITE) {
542 vtty_put_char(vm->vtty_con,(char)*data);
543 d->duart_isr &= ~DUART_TXRDYA;
544 } else {
545 *data = vtty_get_char(vm->vtty_con);
546 d->duart_isr &= ~DUART_RXRDYA;
547 }
548 break;
549
550 case 0x424: /* WRITE: Aux Control Register (ACR) */
551 break;
552
553 case 0x42c: /* Interrupt Status/Mask Register (ISR/IMR) */
554 if (op_type == MTS_WRITE) {
555 d->duart_imr = *data;
556 } else
557 *data = d->duart_isr;
558 break;
559
560 case 0x434: /* Counter/Timer Upper Value (CTU) */
561 case 0x43c: /* Counter/Timer Lower Value (CTL) */
562 case 0x444: /* Mode Register B (MRB) */
563 break;
564
565 case 0x44c: /* Status Register B (SRB) */
566 if (op_type == MTS_READ) {
567 odata = 0;
568
569 if (vtty_is_char_avail(vm->vtty_aux))
570 odata |= DUART_RX_READY;
571
572 odata |= DUART_TX_READY;
573
574 //vm_clear_irq(vm,C7200_DUART_IRQ);
575 *data = odata;
576 }
577 break;
578
579 case 0x454: /* Command Register B (CRB) */
580 /* Disable TX = High */
581 if ((op_type == MTS_WRITE) && (*data & 0x8)) {
582 vm->vtty_aux->managed_flush = TRUE;
583 vtty_flush(vm->vtty_aux);
584 }
585 break;
586
587 case 0x45c: /* RX/TX Holding Register B (RHRB/THRB) */
588 if (op_type == MTS_WRITE) {
589 vtty_put_char(vm->vtty_aux,(char)*data);
590 d->duart_isr &= ~DUART_TXRDYA;
591 } else {
592 *data = vtty_get_char(vm->vtty_aux);
593 d->duart_isr &= ~DUART_RXRDYB;
594 }
595 break;
596
597 case 0x46c: /* WRITE: Output Port Configuration Register (OPCR) */
598 case 0x474: /* READ: Start Counter Command; */
599 /* WRITE: Set Output Port Bits Command */
600 case 0x47c: /* WRITE: Reset Output Port Bits Command */
601 break;
602
603 /* ==== DS 1620 (temp sensors) ==== */
604 case 0x20c: /* Temperature Control */
605 if (op_type == MTS_WRITE)
606 temp_write_ctrl(d,*data);
607 break;
608
609 case 0x214: /* Temperature data write */
610 if (op_type == MTS_WRITE) {
611 temp_write_data(d,*data);
612 d->mux = *data;
613 }
614 break;
615
616 case 0x22c: /* Temperature data read */
617 if (op_type == MTS_READ)
618 *data = temp_read_data(d);
619 break;
620
621 /*
622 * NPE-G1 - Voltages + Power Supplies.
623 * I don't understand exactly how it works, it seems that the low
624 * part must be equal to the high part to have the better values.
625 */
626 case 0x254:
627 #if DEBUG_ENVM
628 vm_log(vm,"ENVM","access to envm a/d converter - mux = %u\n",d->mux);
629 #endif
630 if (op_type == MTS_READ)
631 *data = 0xFFFFFFFF;
632 break;
633
634 case 0x257: /* ENVM A/D Converter */
635 #if DEBUG_ENVM
636 vm_log(vm,"ENVM","access to envm a/d converter - mux = %u\n",d->mux);
637 #endif
638 if (op_type == MTS_READ) {
639 switch(d->mux) {
640 case C7200_MUX_PS0:
641 *data = C7200_A2D_PS0;
642 break;
643
644 case C7200_MUX_PS1:
645 *data = C7200_A2D_PS1;
646 break;
647
648 case C7200_MUX_P3V:
649 *data = C7200_A2D_P3V;
650 break;
651
652 case C7200_MUX_P12V:
653 *data = C7200_A2D_P12V;
654 break;
655
656 case C7200_MUX_P5V:
657 *data = C7200_A2D_P5V;
658 break;
659
660 case C7200_MUX_N12V:
661 *data = C7200_A2D_N12V;
662 break;
663
664 default:
665 *data = 0;
666 }
667
668 *data = *data / C7200_A2D_SAMPLES;
669 }
670 break;
671
672 /* NPE-G2 environmental monitor reading */
673 case 0x3c0:
674 if (op_type == MTS_READ)
675 *data = 0;
676 break;
677
678 case 0x3c4:
679 if (op_type == MTS_WRITE)
680 d->envm_r0 = ntohl(*data);
681 break;
682
683 case 0x3c8:
684 if (op_type == MTS_WRITE) {
685 d->envm_r1 = ntohl(*data);
686 } else {
687 *data = g2_envm_read(d);
688 }
689 break;
690
691 case 0x3cc:
692 if (op_type == MTS_WRITE)
693 d->envm_r2 = ntohl(*data);
694 break;
695
696 /* PCMCIA status ? */
697 case 0x3d6:
698 if (op_type == MTS_READ)
699 *data = 0x33;
700 break;
701
702 #if DEBUG_UNKNOWN
703 default:
704 if (op_type == MTS_READ) {
705 cpu_log(cpu,"IO_FPGA","read from addr 0x%x, pc=0x%llx (size=%u)\n",
706 offset,cpu_get_pc(cpu),op_size);
707 } else {
708 cpu_log(cpu,"IO_FPGA","write to addr 0x%x, value=0x%llx, "
709 "pc=0x%llx (size=%u)\n",
710 offset,*data,cpu_get_pc(cpu),op_size);
711 }
712 #endif
713 }
714
715 IOFPGA_UNLOCK(d);
716 return NULL;
717 }
718
719 /* Initialize system EEPROM groups */
720 void c7200_init_sys_eeprom_groups(c7200_t *router)
721 {
722 router->sys_eeprom_g1 = eeprom_cpu_midplane;
723 router->sys_eeprom_g2 = eeprom_pem_npeb;
724
725 router->sys_eeprom_g1.eeprom[0] = &router->cpu_eeprom;
726 router->sys_eeprom_g1.eeprom[1] = &router->mp_eeprom;
727
728 router->sys_eeprom_g2.eeprom[0] = &router->pem_eeprom;
729 }
730
731 /* Shutdown the IO FPGA device */
732 void dev_c7200_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d)
733 {
734 if (d != NULL) {
735 IOFPGA_LOCK(d);
736 vm->vtty_con->read_notifier = NULL;
737 vm->vtty_aux->read_notifier = NULL;
738 IOFPGA_UNLOCK(d);
739
740 /* Remove the dummy IRQ periodic task */
741 ptask_remove(d->duart_irq_tid);
742
743 /* Remove the device */
744 dev_remove(vm,&d->dev);
745
746 /* Free the structure itself */
747 free(d);
748 }
749 }
750
751 /*
752 * dev_c7200_iofpga_init()
753 */
754 int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len)
755 {
756 vm_instance_t *vm = router->vm;
757 struct iofpga_data *d;
758 u_int i;
759
760 /* Allocate private data structure */
761 if (!(d = malloc(sizeof(*d)))) {
762 fprintf(stderr,"IO_FPGA: out of memory\n");
763 return(-1);
764 }
765
766 memset(d,0,sizeof(*d));
767
768 pthread_mutex_init(&d->lock,NULL);
769 d->router = router;
770
771 for(i=0;i<C7200_TEMP_SENSORS;i++) {
772 d->temp_cfg_reg[i] = DS1620_CONFIG_STATUS_CPU;
773 d->temp_deg_reg[i] = C7200_DEFAULT_TEMP * 2;
774 }
775
776 vm_object_init(&d->vm_obj);
777 d->vm_obj.name = "io_fpga";
778 d->vm_obj.data = d;
779 d->vm_obj.shutdown = (vm_shutdown_t)dev_c7200_iofpga_shutdown;
780
781 /* Set device properties */
782 dev_init(&d->dev);
783 d->dev.name = "io_fpga";
784 d->dev.phys_addr = paddr;
785 d->dev.phys_len = len;
786 d->dev.handler = dev_c7200_iofpga_access;
787 d->dev.priv_data = d;
788
789 /* If we have an I/O slot, we use the I/O slot DUART */
790 if (vm_slot_check_eeprom(vm,0,0)) {
791 vm_log(vm,"CONSOLE","console managed by I/O board\n");
792
793 /* Set console and AUX port notifying functions */
794 vm->vtty_con->priv_data = d;
795 vm->vtty_aux->priv_data = d;
796 vm->vtty_con->read_notifier = tty_con_input;
797 vm->vtty_aux->read_notifier = tty_aux_input;
798
799 /* Trigger periodically a dummy IRQ to flush buffers */
800 d->duart_irq_tid = ptask_add((ptask_callback)tty_trigger_dummy_irq,
801 d,NULL);
802 }
803
804 /* Map this device to the VM */
805 vm_bind_device(vm,&d->dev);
806 vm_object_add(vm,&d->vm_obj);
807 return(0);
808 }

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