/[dynamips]/trunk/dev_c7200_bri.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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upstream/dynamips-0.2.5/dev_c7200_bri.c revision 1 by dpavlin, Sat Oct 6 16:01:44 2007 UTC upstream/dynamips-0.2.7-RC1/dev_c7200_bri.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC
# Line 1  Line 1 
1  /*    /*  
2   * Cisco C7200 (Predator) Simulation Platform.   * Cisco router Simulation Platform.
3   * Copyright (C) 2005-2006 Christophe Fillot.  All rights reserved.   * Copyright (C) 2005-2006 Christophe Fillot.  All rights reserved.
4   *   *
5   * EEPROM types:   * EEPROM types:
# Line 22  Line 22 
22  #include <pthread.h>  #include <pthread.h>
23  #include <assert.h>  #include <assert.h>
24    
25  #include "mips64.h"  #include "cpu.h"
26    #include "vm.h"
27  #include "dynamips.h"  #include "dynamips.h"
28  #include "memory.h"  #include "memory.h"
29  #include "device.h"  #include "device.h"
# Line 285  struct pa_4b_data { Line 286  struct pa_4b_data {
286     u_int m32_offset;     u_int m32_offset;
287  };  };
288    
 /* EEPROM definition (3D = PA-4B, 3E = PA-8B) */  
 static const m_uint16_t eeprom_pa_4b_data[64] = {  
    0x013D, 0x0202, 0xffff, 0xffff, 0x490C, 0x7806, 0x0000, 0x0000,  
    0x5000, 0x0000, 0x0208, 0x1900, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF,  
 };  
   
 static const struct c7200_eeprom eeprom_pa_4b = {  
    "PA-4B", (m_uint16_t *)eeprom_pa_4b_data,  
    sizeof(eeprom_pa_4b_data)/2,  
 };  
   
289  /* Log a PA-4B/PA-8B message */  /* Log a PA-4B/PA-8B message */
290  #define BRI_LOG(d,msg...) vm_log((d)->vm,(d)->name,msg)  #define BRI_LOG(d,msg...) vm_log((d)->vm,(d)->name,msg)
291    
# Line 589  static int m32_action_req(struct m32_dat Line 579  static int m32_action_req(struct m32_dat
579  }  }
580    
581  /* Munich32 general access function */  /* Munich32 general access function */
582  static void *m32_gen_access(struct m32_data *d,cpu_mips_t *cpu,  static void *m32_gen_access(struct m32_data *d,cpu_gen_t *cpu,
583                              m_uint32_t offset,u_int op_size,u_int op_type,                              m_uint32_t offset,u_int op_size,u_int op_type,
584                              m_uint64_t *data)                              m_uint64_t *data)
585  {  {
# Line 652  static void *m32_gen_access(struct m32_d Line 642  static void *m32_gen_access(struct m32_d
642  /*  /*
643   *  pa_4b_access()   *  pa_4b_access()
644   */   */
645  void *pa_4b_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,  void *pa_4b_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
646                     u_int op_size,u_int op_type,m_uint64_t *data)                     u_int op_size,u_int op_type,m_uint64_t *data)
647  {  {
648     struct pa_4b_data *d = dev->priv_data;     struct pa_4b_data *d = dev->priv_data;
# Line 665  void *pa_4b_access(cpu_mips_t *cpu,struc Line 655  void *pa_4b_access(cpu_mips_t *cpu,struc
655     if (offset >= MUNICH32_MEM_SIZE) {     if (offset >= MUNICH32_MEM_SIZE) {
656        if (op_type == MTS_READ) {        if (op_type == MTS_READ) {
657           cpu_log(cpu,d->name,"read  access to offset = 0x%x, pc = 0x%llx "           cpu_log(cpu,d->name,"read  access to offset = 0x%x, pc = 0x%llx "
658                   "(op_size=%u)\n",offset,cpu->pc,op_size);                   "(op_size=%u)\n",offset,cpu_get_pc(cpu),op_size);
659        } else {        } else {
660           cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "           cpu_log(cpu,d->name,"write access to vaddr = 0x%x, pc = 0x%llx, "
661                   "val = 0x%llx (op_size=%u)\n",offset,cpu->pc,*data,op_size);                   "val = 0x%llx (op_size=%u)\n",
662                     offset,cpu_get_pc(cpu),*data,op_size);
663        }        }
664     }     }
665  #endif  #endif
# Line 752  void *pa_4b_access(cpu_mips_t *cpu,struc Line 743  void *pa_4b_access(cpu_mips_t *cpu,struc
743  /*  /*
744   * pci_munich32_read()   * pci_munich32_read()
745   */   */
746  static m_uint32_t pci_munich32_read(cpu_mips_t *cpu,struct pci_device *dev,  static m_uint32_t pci_munich32_read(cpu_gen_t *cpu,struct pci_device *dev,
747                                      int reg)                                      int reg)
748  {    {  
749     struct pa_4b_data *d = dev->priv_data;     struct pa_4b_data *d = dev->priv_data;
# Line 771  static m_uint32_t pci_munich32_read(cpu_ Line 762  static m_uint32_t pci_munich32_read(cpu_
762  /*  /*
763   * pci_munich32_write()   * pci_munich32_write()
764   */   */
765  static void pci_munich32_write(cpu_mips_t *cpu,struct pci_device *dev,  static void pci_munich32_write(cpu_gen_t *cpu,struct pci_device *dev,
766                                 int reg,m_uint32_t value)                                 int reg,m_uint32_t value)
767  {  {
768     struct pa_4b_data *d = dev->priv_data;     struct pa_4b_data *d = dev->priv_data;
# Line 810  int dev_c7200_pa_bri_init(c7200_t *route Line 801  int dev_c7200_pa_bri_init(c7200_t *route
801     d->m32_data.vm = router->vm;     d->m32_data.vm = router->vm;
802    
803     /* Set the EEPROM */     /* Set the EEPROM */
804     c7200_pa_set_eeprom(router,pa_bay,&eeprom_pa_4b);     c7200_pa_set_eeprom(router,pa_bay,cisco_eeprom_find_pa("PA-4B"));
805    
806     /* Add as PCI device PA-4B */     /* Add as PCI device PA-4B */
807     pci_dev = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,     pci_dev = pci_dev_add(router->pa_bay[pa_bay].pci_map,name,
# Line 921  struct c7200_pa_driver dev_c7200_pa_4b_d Line 912  struct c7200_pa_driver dev_c7200_pa_4b_d
912     dev_c7200_pa_bri_shutdown,     dev_c7200_pa_bri_shutdown,
913     dev_c7200_pa_bri_set_nio,     dev_c7200_pa_bri_set_nio,
914     dev_c7200_pa_bri_unset_nio,     dev_c7200_pa_bri_unset_nio,
915       NULL,
916  };  };
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