/[dynamips]/trunk/dev_c7200.h
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Contents of /trunk/dev_c7200.h

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Revision 12 - (show annotations)
Sat Oct 6 16:45:40 2007 UTC (11 years, 7 months ago) by dpavlin
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1 /*
2 * Cisco router simulation platform.
3 * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4 *
5 * Generic Cisco 7200 routines and definitions (EEPROM,...).
6 *
7 * Notes on IRQs (see "show stack"):
8 *
9 * - triggering IRQ 3: we get indefinitely (for each slot):
10 * "Error: Unexpected NM Interrupt received from slot: 6"
11 *
12 * - triggering IRQ 4: GT64010 reg access: probably "DMA/Timer Interrupt"
13 *
14 * - triggering IRQ 6: we get (probably "OIR/Error Interrupt")
15 * %ERR-1-PERR: PCI bus parity error
16 * %ERR-1-SERR: PCI bus system/parity error
17 * %ERR-1-FATAL: Fatal error interrupt, No reloading
18 * err_stat=0x0, err_enable=0x0, mgmt_event=0xFFFFFFFF
19 *
20 */
21
22 #ifndef __DEV_C7200_H__
23 #define __DEV_C7200_H__
24
25 #include <pthread.h>
26
27 #include "utils.h"
28 #include "net.h"
29 #include "device.h"
30 #include "pci_dev.h"
31 #include "nmc93cX6.h"
32 #include "dev_mv64460.h"
33 #include "net_io.h"
34 #include "vm.h"
35
36 /* Default C7200 parameters */
37 #define C7200_DEFAULT_NPE_TYPE "npe-200"
38 #define C7200_DEFAULT_MIDPLANE "vxr"
39 #define C7200_DEFAULT_RAM_SIZE 256
40 #define C7200_DEFAULT_ROM_SIZE 4
41 #define C7200_DEFAULT_NVRAM_SIZE 128
42 #define C7200_DEFAULT_CONF_REG 0x2102
43 #define C7200_DEFAULT_CLOCK_DIV 4
44 #define C7200_DEFAULT_RAM_MMAP 1
45 #define C7200_DEFAULT_DISK0_SIZE 64
46 #define C7200_DEFAULT_DISK1_SIZE 0
47
48 /* 6 slots + 1 I/O card */
49 #define C7200_MAX_PA_BAYS 7
50
51 /* C7200 Timer IRQ (virtual) */
52 #define C7200_VTIMER_IRQ 0
53
54 /* C7200 DUART Interrupt */
55 #define C7200_DUART_IRQ 5
56
57 /* C7200 Network I/O Interrupt */
58 #define C7200_NETIO_IRQ 2
59
60 /* C7200 PA Management Interrupt handler */
61 #define C7200_PA_MGMT_IRQ 3
62
63 /* C7200 GT64k DMA/Timer Interrupt */
64 #define C7200_GT64K_IRQ 4
65
66 /* C7200 Error/OIR Interrupt */
67 #define C7200_OIR_IRQ 6
68
69 /* Network IRQ */
70 #define C7200_NETIO_IRQ_BASE 32
71 #define C7200_NETIO_IRQ_PORT_BITS 3
72 #define C7200_NETIO_IRQ_PORT_MASK ((1 << C7200_NETIO_IRQ_PORT_BITS) - 1)
73 #define C7200_NETIO_IRQ_PER_SLOT (1 << C7200_NETIO_IRQ_PORT_BITS)
74 #define C7200_NETIO_IRQ_END \
75 (C7200_NETIO_IRQ_BASE + (C7200_MAX_PA_BAYS * C7200_NETIO_IRQ_PER_SLOT) - 1)
76
77 /* C7200 base ram limit (256 Mb) */
78 #define C7200_BASE_RAM_LIMIT 256
79
80 /* C7200 common device addresses */
81 #define C7200_GT64K_ADDR 0x14000000ULL
82 #define C7200_GT64K_SEC_ADDR 0x15000000ULL
83 #define C7200_BOOTFLASH_ADDR 0x1a000000ULL
84 #define C7200_NVRAM_ADDR 0x1e000000ULL
85 #define C7200_MPFPGA_ADDR 0x1e800000ULL
86 #define C7200_IOFPGA_ADDR 0x1e840000ULL
87 #define C7200_BITBUCKET_ADDR 0x1f000000ULL
88 #define C7200_ROM_ADDR 0x1fc00000ULL
89 #define C7200_IOMEM_ADDR 0x20000000ULL
90 #define C7200_SRAM_ADDR 0x4b000000ULL
91 #define C7200_BSWAP_ADDR 0xc0000000ULL
92 #define C7200_PCI_IO_ADDR 0x100000000ULL
93
94 /* NPE-G1 specific info */
95 #define C7200_G1_NVRAM_ADDR 0x1e400000ULL
96
97 /* NPE-G2 specific info */
98 #define C7200_G2_BSWAP_ADDR 0xc0000000ULL
99 #define C7200_G2_BOOTFLASH_ADDR 0xe8000000ULL
100 #define C7200_G2_PCI_IO_ADDR 0xf0000000ULL
101 #define C7200_G2_MV64460_ADDR 0xf1000000ULL
102 #define C7200_G2_MPFPGA_ADDR 0xfe000000ULL
103 #define C7200_G2_IOFPGA_ADDR 0xfe040000ULL
104 #define C7200_G2_NVRAM_ADDR 0xff000000ULL
105 #define C7200_G2_ROM_ADDR 0xfff00000ULL
106
107 /* NVRAM size for NPE-G2: 2 Mb */
108 #define C7200_G2_NVRAM_SIZE (2 * 1048576)
109
110 /* Reserved space for ROM in NVRAM */
111 #define C7200_NVRAM_ROM_RES_SIZE 2048
112
113 /* C7200 physical address bus mask: keep only the lower 33 bits */
114 #define C7200_ADDR_BUS_MASK 0x1ffffffffULL
115
116 /* C7200 ELF Platform ID */
117 #define C7200_ELF_MACHINE_ID 0x19
118
119 /* NPE families */
120 enum {
121 C7200_NPE_FAMILY_MIPS = 0,
122 C7200_NPE_FAMILY_PPC,
123 };
124
125 #define VM_C7200(vm) ((c7200_t *)vm->hw_data)
126
127 /* C7200 router */
128 typedef struct c7200_router c7200_t;
129
130 /* Prototype of NPE driver initialization function */
131 typedef int (*c7200_npe_init_fn)(c7200_t *router);
132
133 /* C7200 NPE Driver */
134 struct c7200_npe_driver {
135 char *npe_type;
136 int npe_family;
137 c7200_npe_init_fn npe_init;
138 int max_ram_size;
139 int supported;
140 m_uint64_t nvram_addr;
141 int iocard_required;
142 int clpd6729_pci_bus;
143 int clpd6729_pci_dev;
144 int dec21140_pci_bus;
145 int dec21140_pci_dev;
146 };
147
148 /* C7200 router */
149 struct c7200_router {
150 /* Midplane type (standard,VXR) and chassis MAC address */
151 char *midplane_type;
152 int midplane_version;
153 n_eth_addr_t mac_addr;
154
155 /* Associated VM instance */
156 vm_instance_t *vm;
157
158 /* MV64460 device for NPE-G2 */
159 struct mv64460_data *mv64460_sysctr;
160
161 /* Midplane FPGA */
162 struct c7200_mpfpga_data *mpfpga_data;
163
164 /* NPE and OIR status */
165 struct c7200_npe_driver *npe_driver;
166 m_uint8_t oir_status;
167
168 /* Hidden I/O bridge hack to support PCMCIA */
169 struct pci_bridge *io_pci_bridge;
170 struct pci_bus *pcmcia_bus;
171
172 /* Midplane EEPROM can be modified to change the chassis MAC address... */
173 struct cisco_eeprom cpu_eeprom,mp_eeprom,pem_eeprom;
174
175 struct nmc93cX6_group sys_eeprom_g1; /* EEPROMs for CPU and Midplane */
176 struct nmc93cX6_group sys_eeprom_g2; /* EEPROM for PEM */
177 struct nmc93cX6_group pa_eeprom_g1; /* EEPROMs for bays 0, 1, 3, 4 */
178 struct nmc93cX6_group pa_eeprom_g2; /* EEPROMs for bays 2, 5, 6 */
179 };
180
181 /* Initialize system EEPROM groups */
182 void c7200_init_sys_eeprom_groups(c7200_t *router);
183
184 /* Initialize midplane EEPROM groups */
185 void c7200_init_mp_eeprom_groups(c7200_t *router);
186
187 /* Set EEPROM for the specified slot */
188 int c7200_set_slot_eeprom(c7200_t *router,u_int slot,
189 struct cisco_eeprom *eeprom);
190
191 /* Get network IRQ for specified slot/port */
192 u_int c7200_net_irq_for_slot_port(u_int slot,u_int port);
193
194 /* Show the list of available PA drivers */
195 void c7200_pa_show_drivers(void);
196
197 /* Get an NPE driver */
198 struct c7200_npe_driver *c7200_npe_get_driver(char *npe_type);
199
200 /* Set the NPE type */
201 int c7200_npe_set_type(c7200_t *router,char *npe_type);
202
203 /* Set Midplane type */
204 int c7200_midplane_set_type(c7200_t *router,char *midplane_type);
205
206 /* Set chassis MAC address */
207 int c7200_midplane_set_mac_addr(c7200_t *router,char *mac_addr);
208
209 /* Show C7200 hardware info */
210 void c7200_show_hardware(c7200_t *router);
211
212 /* Trigger an OIR event */
213 int c7200_trigger_oir_event(c7200_t *router,u_int slot_mask);
214
215 /* Initialize a new PA while the virtual router is online (OIR) */
216 int c7200_pa_init_online(c7200_t *router,u_int pa_bay);
217
218 /* Stop a PA while the virtual router is online (OIR) */
219 int c7200_pa_stop_online(c7200_t *router,u_int pa_bay);
220
221 /* dev_c7200_iofpga_init() */
222 int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len);
223
224 /* Register the c7200 platform */
225 int c7200_platform_register(void);
226
227 /* Hypervisor C7200 initialization */
228 extern int hypervisor_c7200_init(vm_platform_t *platform);
229
230 /* PA drivers */
231 extern struct cisco_card_driver dev_c7200_iocard_fe_driver;
232 extern struct cisco_card_driver dev_c7200_iocard_2fe_driver;
233 extern struct cisco_card_driver dev_c7200_iocard_ge_e_driver;
234 extern struct cisco_card_driver dev_c7200_pa_fe_tx_driver;
235 extern struct cisco_card_driver dev_c7200_pa_2fe_tx_driver;
236 extern struct cisco_card_driver dev_c7200_pa_ge_driver;
237 extern struct cisco_card_driver dev_c7200_pa_4e_driver;
238 extern struct cisco_card_driver dev_c7200_pa_8e_driver;
239 extern struct cisco_card_driver dev_c7200_pa_4t_driver;
240 extern struct cisco_card_driver dev_c7200_pa_8t_driver;
241 extern struct cisco_card_driver dev_c7200_pa_a1_driver;
242 extern struct cisco_card_driver dev_c7200_pa_pos_oc3_driver;
243 extern struct cisco_card_driver dev_c7200_pa_4b_driver;
244 extern struct cisco_card_driver dev_c7200_pa_mc8te1_driver;
245
246 #endif

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