/[dynamips]/trunk/dev_c7200.c
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upstream/dynamips-0.2.6-RC5/dev_c7200.c revision 6 by dpavlin, Sat Oct 6 16:09:07 2007 UTC upstream/dynamips-0.2.7/dev_c7200.c revision 10 by dpavlin, Sat Oct 6 16:29:14 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   * Cisco 7200 (Predator) simulation platform.   * Cisco router simulation platform.
3   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)   * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4   *   *
5   * Generic Cisco 7200 routines and definitions (EEPROM,...).   * Generic Cisco 7200 routines and definitions (EEPROM,...).
# Line 12  Line 12 
12  #include <sys/types.h>  #include <sys/types.h>
13  #include <assert.h>  #include <assert.h>
14    
15  #include "mips64.h"  #include "cpu.h"
16    #include "vm.h"
17  #include "dynamips.h"  #include "dynamips.h"
18  #include "memory.h"  #include "memory.h"
19    #include "ppc32_mem.h"
20  #include "device.h"  #include "device.h"
21  #include "pci_io.h"  #include "pci_io.h"
22  #include "dev_gt.h"  #include "dev_gt.h"
23    #include "dev_mv64460.h"
24  #include "cisco_eeprom.h"  #include "cisco_eeprom.h"
25    #include "dev_rom.h"
26  #include "dev_c7200.h"  #include "dev_c7200.h"
27    #include "dev_c7200_mpfpga.h"
28  #include "dev_vtty.h"  #include "dev_vtty.h"
29  #include "registry.h"  #include "registry.h"
30  #include "net.h"  #include "net.h"
# Line 88  static m_uint16_t eeprom_cpu_npeg1_data[ Line 93  static m_uint16_t eeprom_cpu_npeg1_data[
93     0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,     0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
94  };  };
95    
96    /* NPE-G2 */
97    static m_uint16_t eeprom_cpu_npeg2_data[64] = {
98       0x04FF, 0x4004, 0xCA41, 0x0201, 0x8744, 0x19BC, 0x0182, 0x4928,
99       0x5901, 0x42FF, 0xFFC1, 0x8B43, 0x534A, 0x3039, 0x3435, 0x3239,
100       0x3237, 0x0400, 0x0201, 0x851C, 0x1DA2, 0x01CB, 0x864E, 0x5045,
101       0x2D47, 0x3280, 0x0000, 0x0000, 0x8956, 0x3031, 0x2DFF, 0xFFFF,
102       0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
103       0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
104       0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
105       0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x15FF,
106    };
107    
108  /*  /*
109   * CPU EEPROM array.   * CPU EEPROM array.
110   */   */
# Line 100  static struct cisco_eeprom c7200_cpu_eep Line 117  static struct cisco_eeprom c7200_cpu_eep
117     { "npe-300", eeprom_cpu_npe300_data, sizeof(eeprom_cpu_npe300_data)/2 },     { "npe-300", eeprom_cpu_npe300_data, sizeof(eeprom_cpu_npe300_data)/2 },
118     { "npe-400", eeprom_cpu_npe400_data, sizeof(eeprom_cpu_npe400_data)/2 },     { "npe-400", eeprom_cpu_npe400_data, sizeof(eeprom_cpu_npe400_data)/2 },
119     { "npe-g1" , eeprom_cpu_npeg1_data , sizeof(eeprom_cpu_npeg1_data)/2 },     { "npe-g1" , eeprom_cpu_npeg1_data , sizeof(eeprom_cpu_npeg1_data)/2 },
120       { "npe-g2" , eeprom_cpu_npeg2_data , sizeof(eeprom_cpu_npeg2_data)/2 },
121     { NULL, NULL, 0 },     { NULL, NULL, 0 },
122  };  };
123    
# Line 161  static struct cisco_eeprom c7200_pem_eep Line 179  static struct cisco_eeprom c7200_pem_eep
179  /* Port Adapter Drivers                                                     */  /* Port Adapter Drivers                                                     */
180  /* ======================================================================== */  /* ======================================================================== */
181  static struct c7200_pa_driver *pa_drivers[] = {  static struct c7200_pa_driver *pa_drivers[] = {
182     &dev_c7200_io_fe_driver,     &dev_c7200_iocard_fe_driver,
183       &dev_c7200_iocard_2fe_driver,
184       &dev_c7200_iocard_ge_e_driver,
185     &dev_c7200_pa_fe_tx_driver,     &dev_c7200_pa_fe_tx_driver,
186       &dev_c7200_pa_2fe_tx_driver,
187       &dev_c7200_pa_ge_driver,
188     &dev_c7200_pa_4e_driver,     &dev_c7200_pa_4e_driver,
189     &dev_c7200_pa_8e_driver,     &dev_c7200_pa_8e_driver,
190     &dev_c7200_pa_4t_driver,     &dev_c7200_pa_4t_driver,
# Line 188  DECLARE_NPE(npe225); Line 210  DECLARE_NPE(npe225);
210  DECLARE_NPE(npe300);  DECLARE_NPE(npe300);
211  DECLARE_NPE(npe400);  DECLARE_NPE(npe400);
212  DECLARE_NPE(npeg1);  DECLARE_NPE(npeg1);
213    DECLARE_NPE(npeg2);
214    
215  static struct c7200_npe_driver npe_drivers[] = {  static struct c7200_npe_driver npe_drivers[] = {
216     { "npe-100" , c7200_init_npe100, 256, 1, C7200_NVRAM_ADDR, 0, 5,  0, 6 },     { "npe-100" , C7200_NPE_FAMILY_MIPS, c7200_init_npe100, 256, 1,
217     { "npe-150" , c7200_init_npe150, 256, 1, C7200_NVRAM_ADDR, 0, 5,  0, 6 },       C7200_NVRAM_ADDR, TRUE, 0, 5,  0, 6 },
218     { "npe-175" , c7200_init_npe175, 256, 1, C7200_NVRAM_ADDR, 2, 16, 1, 0 },     { "npe-150" , C7200_NPE_FAMILY_MIPS, c7200_init_npe150, 256, 1,
219     { "npe-200" , c7200_init_npe200, 256, 1, C7200_NVRAM_ADDR, 0, 5,  0, 6 },       C7200_NVRAM_ADDR, TRUE, 0, 5,  0, 6 },
220     { "npe-225" , c7200_init_npe225, 256, 1, C7200_NVRAM_ADDR, 2, 16, 1, 0 },     { "npe-175" , C7200_NPE_FAMILY_MIPS, c7200_init_npe175, 256, 1,
221     { "npe-300" , c7200_init_npe300, 256, 1, C7200_NVRAM_ADDR, 2, 16, 1, 0 },       C7200_NVRAM_ADDR, TRUE, 2, 16, 1, 0 },
222     { "npe-400" , c7200_init_npe400, 512, 1, C7200_NVRAM_ADDR, 2, 16, 1, 0 },     { "npe-200" , C7200_NPE_FAMILY_MIPS, c7200_init_npe200, 256, 1,
223     { "npe-g1"  , c7200_init_npeg1, 1024, 0,       C7200_NVRAM_ADDR, TRUE, 0, 5,  0, 6 },
224       C7200_NPEG1_NVRAM_ADDR, 17, 16, 16, 0 },     { "npe-225" , C7200_NPE_FAMILY_MIPS, c7200_init_npe225, 256, 1,
225     { NULL      , NULL },       C7200_NVRAM_ADDR, TRUE, 2, 16, 1, 0 },
226       { "npe-300" , C7200_NPE_FAMILY_MIPS, c7200_init_npe300, 256, 1,
227         C7200_NVRAM_ADDR, TRUE, 2, 16, 1, 0 },
228       { "npe-400" , C7200_NPE_FAMILY_MIPS, c7200_init_npe400, 512, 1,
229         C7200_NVRAM_ADDR, TRUE, 2, 16, 1, 0 },
230       { "npe-g1"  , C7200_NPE_FAMILY_MIPS, c7200_init_npeg1, 1024, 0,
231         C7200_G1_NVRAM_ADDR, FALSE, 17, 16, 16, 0 },
232       { "npe-g2"  , C7200_NPE_FAMILY_PPC , c7200_init_npeg2, 1024, 0,
233         C7200_G2_NVRAM_ADDR, FALSE, 17, 16, 16, 0 },
234       { NULL, -1, NULL, -1, -1, 0, -1, -1, -1, -1 },
235  };  };
236    
237  /* ======================================================================== */  /* ======================================================================== */
# Line 502  void c7200_save_config_all(FILE *fd) Line 534  void c7200_save_config_all(FILE *fd)
534     registry_foreach_type(OBJ_TYPE_VM,c7200_reg_save_config,fd,NULL);     registry_foreach_type(OBJ_TYPE_VM,c7200_reg_save_config,fd,NULL);
535  }  }
536    
537    /* Get slot/port corresponding to specified network IRQ */
538    static inline void
539    c7200_net_irq_get_slot_port(u_int irq,u_int *slot,u_int *port)
540    {
541       irq -= C7200_NETIO_IRQ_BASE;
542       *port = irq & C7200_NETIO_IRQ_PORT_MASK;
543       *slot = irq >> C7200_NETIO_IRQ_PORT_BITS;
544    }
545    
546    /* Get network IRQ for specified slot/port */
547    u_int c7200_net_irq_for_slot_port(u_int slot,u_int port)
548    {
549       u_int irq;
550    
551       irq = (slot << C7200_NETIO_IRQ_PORT_BITS) + port;
552       irq += C7200_NETIO_IRQ_BASE;
553    
554       return(irq);
555    }
556    
557  /* Set NPE eeprom definition */  /* Set NPE eeprom definition */
558  static int c7200_npe_set_eeprom(c7200_t *router)  static int c7200_npe_set_eeprom(c7200_t *router)
559  {  {
# Line 572  int c7200_pa_unset_eeprom(c7200_t *route Line 624  int c7200_pa_unset_eeprom(c7200_t *route
624  /* Check if a bay has a port adapter */  /* Check if a bay has a port adapter */
625  int c7200_pa_check_eeprom(c7200_t *router,u_int pa_bay)  int c7200_pa_check_eeprom(c7200_t *router,u_int pa_bay)
626  {  {
627     if (!pa_bay || (pa_bay >= C7200_MAX_PA_BAYS))     if (pa_bay >= C7200_MAX_PA_BAYS)
628        return(FALSE);        return(FALSE);
629    
630     return(cisco_eeprom_valid(&router->pa_bay[pa_bay].eeprom));     return(cisco_eeprom_valid(&router->pa_bay[pa_bay].eeprom));
# Line 896  int c7200_pa_init(c7200_t *router,u_int Line 948  int c7200_pa_init(c7200_t *router,u_int
948     snprintf(bay->dev_name,len,"%s(%u)",bay->dev_type,pa_bay);     snprintf(bay->dev_name,len,"%s(%u)",bay->dev_type,pa_bay);
949    
950     /* Initialize PA driver */     /* Initialize PA driver */
951     if (bay->pa_driver->pa_init(router,bay->dev_name,pa_bay) == 1) {     if (bay->pa_driver->pa_init(router,bay->dev_name,pa_bay) == -1) {
952        vm_error(router->vm,"unable to initialize PA %u.\n",pa_bay);        vm_error(router->vm,"unable to initialize PA %u.\n",pa_bay);
953        return(-1);        return(-1);
954     }     }
# Line 1318  static int c7200_init_dual_gt64120(c7200 Line 1370  static int c7200_init_dual_gt64120(c7200
1370     return(0);     return(0);
1371  }  }
1372    
1373    /* Create the two main PCI busses for a MV64460 based system */
1374    static int c7200_init_mv64460(c7200_t *router)
1375    {
1376       vm_instance_t *vm = router->vm;
1377    
1378       vm->pci_bus[0] = pci_bus_create("MB0/MB1",3);
1379       vm->pci_bus[1] = pci_bus_create("MB2",0);
1380    
1381       if (!vm->pci_bus[0] || !vm->pci_bus[1]) {
1382          vm_error(vm,"unable to create PCI data.\n");
1383          return(-1);
1384       }
1385    
1386       return(dev_mv64460_init(vm,"mv64460",C7200_G2_MV64460_ADDR,0x10000));
1387    }
1388    
1389  /* Create the PA PCI busses */  /* Create the PA PCI busses */
1390  static int c7200_pa_create_pci_busses(c7200_t *router)  static int c7200_pa_create_pci_busses(c7200_t *router)
1391  {    {  
# Line 1393  int c7200_init_npe100(c7200_t *router) Line 1461  int c7200_init_npe100(c7200_t *router)
1461     int i;     int i;
1462    
1463     /* Set the processor type: R4600 */     /* Set the processor type: R4600 */
1464     mips64_set_prid(vm->boot_cpu,MIPS_PRID_R4600);     mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R4600);
1465    
1466     /* Initialize the Galileo GT-64010 system controller */     /* Initialize the Galileo GT-64010 system controller */
1467     if (c7200_init_gt64010(router) == -1)     if (c7200_init_gt64010(router) == -1)
# Line 1441  int c7200_init_npe150(c7200_t *router) Line 1509  int c7200_init_npe150(c7200_t *router)
1509     int i;     int i;
1510    
1511     /* Set the processor type: R4700 */     /* Set the processor type: R4700 */
1512     mips64_set_prid(vm->boot_cpu,MIPS_PRID_R4700);     mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R4700);
1513    
1514     /* Initialize the Galileo GT-64010 system controller */     /* Initialize the Galileo GT-64010 system controller */
1515     if (c7200_init_gt64010(router) == -1)     if (c7200_init_gt64010(router) == -1)
# Line 1497  int c7200_init_npe175(c7200_t *router) Line 1565  int c7200_init_npe175(c7200_t *router)
1565     int i;     int i;
1566    
1567     /* Set the processor type: R5271 */     /* Set the processor type: R5271 */
1568     mips64_set_prid(vm->boot_cpu,MIPS_PRID_R527x);     mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R527x);
1569    
1570     /* Initialize the Galileo GT-64120 PCI controller */     /* Initialize the Galileo GT-64120 PCI controller */
1571     if (c7200_init_gt64120(router) == -1)     if (c7200_init_gt64120(router) == -1)
# Line 1542  int c7200_init_npe200(c7200_t *router) Line 1610  int c7200_init_npe200(c7200_t *router)
1610     int i;     int i;
1611    
1612     /* Set the processor type: R5000 */     /* Set the processor type: R5000 */
1613     mips64_set_prid(vm->boot_cpu,MIPS_PRID_R5000);     mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R5000);
1614    
1615     /* Initialize the Galileo GT-64010 PCI controller */     /* Initialize the Galileo GT-64010 PCI controller */
1616     if (c7200_init_gt64010(router) == -1)     if (c7200_init_gt64010(router) == -1)
# Line 1598  int c7200_init_npe225(c7200_t *router) Line 1666  int c7200_init_npe225(c7200_t *router)
1666     int i;     int i;
1667    
1668     /* Set the processor type: R5271 */     /* Set the processor type: R5271 */
1669     mips64_set_prid(vm->boot_cpu,MIPS_PRID_R527x);     mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R527x);
1670    
1671     /* Initialize the Galileo GT-64120 PCI controller */     /* Initialize the Galileo GT-64120 PCI controller */
1672     if (c7200_init_gt64120(router) == -1)     if (c7200_init_gt64120(router) == -1)
# Line 1642  int c7200_init_npe300(c7200_t *router) Line 1710  int c7200_init_npe300(c7200_t *router)
1710     int i;     int i;
1711    
1712     /* Set the processor type: R7000 */     /* Set the processor type: R7000 */
1713     mips64_set_prid(vm->boot_cpu,MIPS_PRID_R7000);     mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R7000);
1714    
1715     /* 32 Mb of I/O memory */     /* 32 Mb of I/O memory */
1716     vm->iomem_size = 32;     vm->iomem_size = 32;
1717     dev_ram_init(vm,"iomem",vm->ram_mmap,TRUE,NULL,C7200_IOMEM_ADDR,32*1048576);     dev_ram_init(vm,"iomem",vm->ram_mmap,TRUE,NULL,vm->sparse_mem,
1718                    C7200_IOMEM_ADDR,32*1048576);
1719    
1720     /* Initialize the two Galileo GT-64120 system controllers */     /* Initialize the two Galileo GT-64120 system controllers */
1721     if (c7200_init_dual_gt64120(router) == -1)     if (c7200_init_dual_gt64120(router) == -1)
# Line 1695  int c7200_init_npe400(c7200_t *router) Line 1764  int c7200_init_npe400(c7200_t *router)
1764     int i;     int i;
1765    
1766     /* Set the processor type: R7000 */     /* Set the processor type: R7000 */
1767     mips64_set_prid(vm->boot_cpu,MIPS_PRID_R7000);     mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_R7000);
1768    
1769     /*     /*
1770      * Add supplemental memory (as "iomem") if we have more than 256 Mb.      * Add supplemental memory (as "iomem") if we have more than 256 Mb.
# Line 1703  int c7200_init_npe400(c7200_t *router) Line 1772  int c7200_init_npe400(c7200_t *router)
1772     if (vm->ram_size > C7200_BASE_RAM_LIMIT) {     if (vm->ram_size > C7200_BASE_RAM_LIMIT) {
1773        vm->iomem_size = vm->ram_size - C7200_BASE_RAM_LIMIT;        vm->iomem_size = vm->ram_size - C7200_BASE_RAM_LIMIT;
1774        vm->ram_size = C7200_BASE_RAM_LIMIT;        vm->ram_size = C7200_BASE_RAM_LIMIT;
1775        dev_ram_init(vm,"ram1",vm->ram_mmap,TRUE,NULL,        dev_ram_init(vm,"ram1",vm->ram_mmap,TRUE,NULL,vm->sparse_mem,
1776                     C7200_IOMEM_ADDR,vm->iomem_size*1048576);                     C7200_IOMEM_ADDR,vm->iomem_size*1048576);
1777     }     }
1778    
# Line 1746  int c7200_init_npeg1(c7200_t *router) Line 1815  int c7200_init_npeg1(c7200_t *router)
1815     int i;     int i;
1816    
1817     /* Just some tests */     /* Just some tests */
1818     mips64_set_prid(vm->boot_cpu,MIPS_PRID_BCM1250);     mips64_set_prid(CPU_MIPS64(vm->boot_cpu),MIPS_PRID_BCM1250);
1819     vm->pci_bus[0] = pci_bus_create("HT/PCI bus",0);     vm->pci_bus[0] = pci_bus_create("HT/PCI bus",0);
1820    
1821     /* SB-1 System control devices */     /* SB-1 System control devices */
# Line 1797  int c7200_init_npeg1(c7200_t *router) Line 1866  int c7200_init_npeg1(c7200_t *router)
1866     return(0);     return(0);
1867  }  }
1868    
1869    /* Initialize an NPE-G2 board (XXX not working) */
1870    int c7200_init_npeg2(c7200_t *router)
1871    {    
1872       vm_instance_t *vm = router->vm;
1873       int i;
1874    
1875       /* Set the processor type: PowerPC G4 */
1876       ppc32_set_pvr(CPU_PPC32(vm->boot_cpu),0x80040201);
1877    
1878       /* Initialize the PA PCI busses */
1879       if (c7200_pa_create_pci_busses(router) == -1)
1880          return(-1);
1881    
1882       /* Create PCI bus for PA Bay 0 (I/O Card, PCMCIA, Interfaces) */
1883       vm->pci_bus_pool[0] = pci_bus_create("PA Slot 0",-1);
1884    
1885       /* PCI bridge for I/O card device on MB0 */
1886       dev_plx6520cb_init(vm->pci_bus[1],3,vm->pci_bus_pool[0]);
1887    
1888       /* Create PCI busses for PA Bays 1,3,5 and PA Bays 2,4,6 */
1889       vm->pci_bus_pool[24] = pci_bus_create("PA Slots 1,3,5",-1);
1890       vm->pci_bus_pool[25] = pci_bus_create("PA Slots 2,4,6",-1);
1891    
1892       dev_plx6520cb_init(vm->pci_bus[0],1,vm->pci_bus_pool[24]);
1893       dev_plx6520cb_init(vm->pci_bus[0],2,vm->pci_bus_pool[25]);
1894    
1895       /* Create the hidden "I/O" PCI bridge for PCMCIA controller */
1896       c7200_create_io_pci_bridge(router,vm->pci_bus_pool[0]);
1897    
1898       /* Map the PA PCI busses */
1899       router->pa_bay[0].pci_map = vm->pci_bus_pool[0];
1900    
1901       for(i=1;i<C7200_MAX_PA_BAYS;i++)
1902          router->pa_bay[i].pci_map = vm->pci_bus_pool[i];
1903    
1904       /* PCI bridges for PA Bays 1 to 6 */
1905       c7200_pa_init_pci_bridge(router,1,vm->pci_bus_pool[24],1);
1906       c7200_pa_init_pci_bridge(router,3,vm->pci_bus_pool[24],2);
1907       c7200_pa_init_pci_bridge(router,5,vm->pci_bus_pool[24],3);
1908    
1909       c7200_pa_init_pci_bridge(router,2,vm->pci_bus_pool[25],1);
1910       c7200_pa_init_pci_bridge(router,4,vm->pci_bus_pool[25],2);
1911       c7200_pa_init_pci_bridge(router,6,vm->pci_bus_pool[25],3);
1912       return(0);
1913    }
1914    
1915  /* Show C7200 hardware info */  /* Show C7200 hardware info */
1916  void c7200_show_hardware(c7200_t *router)  void c7200_show_hardware(c7200_t *router)
1917  {  {
# Line 1860  void c7200_init_defaults(c7200_t *router Line 1975  void c7200_init_defaults(c7200_t *router
1975  }  }
1976    
1977  /* Run the checklist */  /* Run the checklist */
1978  int c7200_checklist(c7200_t *router)  static int c7200_checklist(c7200_t *router)
1979  {  {
1980     struct vm_instance *vm = router->vm;     struct vm_instance *vm = router->vm;
1981     int res = 0;     int res = 0;
# Line 1876  int c7200_checklist(c7200_t *router) Line 1991  int c7200_checklist(c7200_t *router)
1991     return(res);     return(res);
1992  }  }
1993    
1994  /* Initialize the C7200 Platform */  /* Initialize Port Adapters */
1995  int c7200_init_platform(c7200_t *router)  static int c7200_init_platform_pa(c7200_t *router)
1996  {  {
1997     struct vm_instance *vm = router->vm;     vm_instance_t *vm = router->vm;
1998     struct c7200_pa_bay *pa_bay;     struct c7200_pa_bay *pa_bay;
    cpu_mips_t *cpu0;  
1999     int i;     int i;
2000    
2001       /* Initialize Port Adapters */
2002       for(i=0;i<C7200_MAX_PA_BAYS;i++) {
2003          pa_bay = &router->pa_bay[i];
2004    
2005          if (!pa_bay->dev_type)
2006             continue;
2007    
2008          if (c7200_pa_init(router,i) == -1) {
2009             vm_error(vm,"unable to create Port Adapter \"%s\"\n",
2010                      pa_bay->dev_type);
2011             return(-1);
2012          }
2013       }
2014    
2015       /*
2016        * By default, initialize a C7200-IO-FE in slot 0 if nothing found.
2017        * We only do that for NPEs that require an IO card (all excepted G1/G2).
2018        */
2019       if (router->npe_driver->iocard_required && !router->pa_bay[0].drv_info) {
2020          c7200_pa_add_binding(router,"C7200-IO-FE",0);
2021          c7200_pa_init(router,0);
2022       }
2023    
2024       return(0);
2025    }
2026    
2027    /* Initialize the C7200 Platform (MIPS) */
2028    static int c7200m_init_platform(c7200_t *router)
2029    {
2030       struct vm_instance *vm = router->vm;
2031       cpu_mips_t *cpu0;
2032       cpu_gen_t *gen0;
2033       vm_obj_t *obj;
2034    
2035     /* Copy config register setup into "active" config register */     /* Copy config register setup into "active" config register */
2036     vm->conf_reg = vm->conf_reg_setup;     vm->conf_reg = vm->conf_reg_setup;
2037    
# Line 1903  int c7200_init_platform(c7200_t *router) Line 2051  int c7200_init_platform(c7200_t *router)
2051     vm->cpu_group = cpu_group_create("System CPU");     vm->cpu_group = cpu_group_create("System CPU");
2052    
2053     /* Initialize the virtual MIPS processor */     /* Initialize the virtual MIPS processor */
2054     if (!(cpu0 = cpu_create(vm,0))) {     if (!(gen0 = cpu_create(vm,CPU_TYPE_MIPS64,0))) {
2055        vm_error(vm,"unable to create CPU0!\n");        vm_error(vm,"unable to create CPU0!\n");
2056        return(-1);        return(-1);
2057     }     }
2058    
2059       cpu0 = CPU_MIPS64(gen0);
2060    
2061     /* Add this CPU to the system CPU group */     /* Add this CPU to the system CPU group */
2062     cpu_group_add(vm->cpu_group,cpu0);     cpu_group_add(vm->cpu_group,gen0);
2063     vm->boot_cpu = cpu0;     vm->boot_cpu = gen0;
2064    
2065       /* Initialize the IRQ routing vectors */
2066       vm->set_irq = mips64_vm_set_irq;
2067       vm->clear_irq = mips64_vm_clear_irq;
2068    
2069     /* Mark the Network IO interrupt as high priority */     /* Mark the Network IO interrupt as high priority */
2070     cpu0->irq_idle_preempt[C7200_NETIO_IRQ] = TRUE;     cpu0->irq_idle_preempt[C7200_NETIO_IRQ] = TRUE;
# Line 1941  int c7200_init_platform(c7200_t *router) Line 2095  int c7200_init_platform(c7200_t *router)
2095     /* Bit-bucket zone */     /* Bit-bucket zone */
2096     dev_zero_init(vm,"zero",C7200_BITBUCKET_ADDR,0xc00000);     dev_zero_init(vm,"zero",C7200_BITBUCKET_ADDR,0xc00000);
2097    
2098       /* Initialize the NPE board */
2099       if (router->npe_driver->npe_init(router) == -1)
2100          return(-1);
2101    
2102       /* Initialize RAM */
2103       vm_ram_init(vm,0x00000000ULL);
2104    
2105       /* Initialize ROM */
2106       if (!vm->rom_filename) {
2107          /* use embedded ROM */
2108          dev_rom_init(vm,"rom",C7200_ROM_ADDR,vm->rom_size*1048576,
2109                       mips64_microcode,mips64_microcode_len);
2110       } else {
2111          /* use alternate ROM */
2112          dev_ram_init(vm,"rom",TRUE,TRUE,NULL,FALSE,
2113                       C7200_ROM_ADDR,vm->rom_size*1048576);
2114       }
2115    
2116       /* Byte swapping */
2117       dev_bswap_init(vm,"mem_bswap",C7200_BSWAP_ADDR,1024*1048576,0x00000000ULL);
2118    
2119       /* PCI IO space */
2120       if (!(vm->pci_io_space = pci_io_data_init(vm,C7200_PCI_IO_ADDR)))
2121          return(-1);
2122    
2123       /* Cirrus Logic PD6729 (PCI-to-PCMCIA host adapter) */
2124       dev_clpd6729_init(vm,router->pcmcia_bus,
2125                         router->npe_driver->clpd6729_pci_dev,
2126                         vm->pci_io_space,0x402,0x403);
2127    
2128       /* Initialize the Port Adapters */
2129       if (c7200_init_platform_pa(router) == -1)
2130          return(-1);
2131    
2132       /* Verify the check list */
2133       if (c7200_checklist(router) == -1)
2134          return(-1);
2135    
2136     /* Midplane FPGA */     /* Midplane FPGA */
2137     dev_c7200_mpfpga_init(router,C7200_MPFPGA_ADDR,0x1000);     dev_c7200_mpfpga_init(router,C7200_MPFPGA_ADDR,0x1000);
2138    
2139       if (!(obj = vm_object_find(router->vm,"mp_fpga")))
2140          return(-1);
2141    
2142       router->mpfpga_data = obj->data;
2143    
2144     /* IO FPGA */     /* IO FPGA */
2145     if (dev_c7200_iofpga_init(router,C7200_IOFPGA_ADDR,0x1000) == -1)     if (dev_c7200_iofpga_init(router,C7200_IOFPGA_ADDR,0x1000) == -1)
2146        return(-1);        return(-1);
2147    
2148       /* Show device list */
2149       c7200_show_hardware(router);
2150       return(0);
2151    }
2152    
2153    /* Initialize the C7200 Platform (PowerPC) */
2154    static int c7200p_init_platform(c7200_t *router)
2155    {
2156       struct vm_instance *vm = router->vm;
2157       cpu_ppc_t *cpu0;
2158       cpu_gen_t *gen0;
2159       vm_obj_t *obj;
2160    
2161       /* Copy config register setup into "active" config register */
2162       vm->conf_reg = vm->conf_reg_setup;
2163    
2164       /* Create Console and AUX ports */
2165       vm_init_vtty(vm);
2166    
2167       /* Check that the amount of RAM is valid */
2168       if (vm->ram_size > router->npe_driver->max_ram_size) {
2169          vm_error(vm,"%u is not a valid RAM size for this NPE. "
2170                   "Fallback to %u Mb.\n\n",
2171                   vm->ram_size,router->npe_driver->max_ram_size);
2172      
2173          vm->ram_size = router->npe_driver->max_ram_size;
2174       }
2175    
2176       /* Create a CPU group */
2177       vm->cpu_group = cpu_group_create("System CPU");
2178    
2179       /* Initialize the virtual PowerPC processor */
2180       if (!(gen0 = cpu_create(vm,CPU_TYPE_PPC32,0))) {
2181          vm_error(vm,"unable to create CPU0!\n");
2182          return(-1);
2183       }
2184    
2185       cpu0 = CPU_PPC32(gen0);
2186    
2187       /* Add this CPU to the system CPU group */
2188       cpu_group_add(vm->cpu_group,gen0);
2189       vm->boot_cpu = gen0;
2190    
2191       /* Mark the Network IO interrupt as high priority */
2192       vm->irq_idle_preempt[C7200_NETIO_IRQ] = TRUE;
2193    
2194       /* Copy some parameters from VM to CPU0 (idle PC, ...) */
2195       cpu0->idle_pc = vm->idle_pc;
2196    
2197       if (vm->timer_irq_check_itv)
2198          cpu0->timer_irq_check_itv = vm->timer_irq_check_itv;
2199    
2200       /* Initialize the Marvell MV-64460 system controller */
2201       if (c7200_init_mv64460(router) == -1)
2202          return(-1);
2203    
2204       if (!(obj = vm_object_find(router->vm,"mv64460")))
2205          return(-1);
2206    
2207       router->mv64460_sysctr = obj->data;
2208    
2209       /* Remote emulator control */
2210       dev_remote_control_init(vm,0xf6000000,0x1000);
2211    
2212       /* Bootflash */
2213       dev_bootflash_init(vm,"bootflash",C7200_G2_BOOTFLASH_ADDR,(64 * 1048576));
2214    
2215       /* NVRAM and calendar */
2216       vm->nvram_size = C7200_G2_NVRAM_SIZE / 1024;
2217       dev_nvram_init(vm,"nvram",router->npe_driver->nvram_addr,
2218                      C7200_G2_NVRAM_SIZE,&vm->conf_reg);
2219    
2220     /* Initialize the NPE board */     /* Initialize the NPE board */
2221     if (router->npe_driver->npe_init(router) == -1)     if (router->npe_driver->npe_init(router) == -1)
2222        return(-1);        return(-1);
# Line 1958  int c7200_init_platform(c7200_t *router) Line 2227  int c7200_init_platform(c7200_t *router)
2227     /* Initialize ROM */     /* Initialize ROM */
2228     if (!vm->rom_filename) {     if (!vm->rom_filename) {
2229        /* use embedded ROM */        /* use embedded ROM */
2230        dev_rom_init(vm,"rom",C7200_ROM_ADDR,vm->rom_size*1048576);        dev_rom_init(vm,"rom",C7200_G2_ROM_ADDR,vm->rom_size*1048576,
2231                       ppc32_microcode,ppc32_microcode_len);
2232     } else {     } else {
2233        /* use alternate ROM */        /* use alternate ROM */
2234        dev_ram_init(vm,"rom",TRUE,TRUE,NULL,        dev_ram_init(vm,"rom",TRUE,TRUE,NULL,FALSE,
2235                     C7200_ROM_ADDR,vm->rom_size*1048576);                     C7200_G2_ROM_ADDR,vm->rom_size*1048576);
2236     }     }
2237    
2238       /* Byte swapping */
2239       dev_bswap_init(vm,"mem_bswap",C7200_G2_BSWAP_ADDR,512*1048576,
2240                      0x00000000ULL);
2241    
2242     /* PCI IO space */     /* PCI IO space */
2243     if (!(vm->pci_io_space = pci_io_data_init(vm,C7200_PCI_IO_ADDR)))     if (!(vm->pci_io_space = pci_io_data_init(vm,C7200_G2_PCI_IO_ADDR)))
2244        return(-1);        return(-1);
2245    
2246     /* Cirrus Logic PD6729 (PCI-to-PCMCIA host adapter) */     /* Cirrus Logic PD6729 (PCI-to-PCMCIA host adapter) */
# Line 1974  int c7200_init_platform(c7200_t *router) Line 2248  int c7200_init_platform(c7200_t *router)
2248                       router->npe_driver->clpd6729_pci_dev,                       router->npe_driver->clpd6729_pci_dev,
2249                       vm->pci_io_space,0x402,0x403);                       vm->pci_io_space,0x402,0x403);
2250    
2251     /* Initialize Port Adapters */     /* Initialize the Port Adapters */
2252     for(i=0;i<C7200_MAX_PA_BAYS;i++) {     if (c7200_init_platform_pa(router) == -1)
2253        pa_bay = &router->pa_bay[i];        return(-1);
2254      
2255       /* IO FPGA */
2256       if (dev_c7200_iofpga_init(router,C7200_G2_IOFPGA_ADDR,0x1000) == -1)
2257          return(-1);
2258    
2259        if (!pa_bay->dev_type)     /* MP FPGA */
2260           continue;     if (dev_c7200_mpfpga_init(router,C7200_G2_MPFPGA_ADDR,0x10000) == -1)
2261          return(-1);
2262    
2263        if (c7200_pa_init(router,i) == -1) {     if (!(obj = vm_object_find(router->vm,"mp_fpga")))
2264           vm_error(vm,"unable to create Port Adapter \"%s\"\n",        return(-1);
                   pa_bay->dev_type);  
          return(-1);  
       }  
    }  
2265    
2266     /* By default, initialize a C7200-IO-FE in slot 0 if nothing found */     router->mpfpga_data = obj->data;
    if (!router->pa_bay[0].drv_info) {  
       c7200_pa_add_binding(router,"C7200-IO-FE",0);  
       c7200_pa_init(router,0);  
    }  
2267    
2268     /* Verify the check list */     /* If we have nothing in slot 0, the console is handled by the MV64460 */
2269     if (c7200_checklist(router) == -1)     if (!c7200_pa_check_eeprom(router,0)) {
2270        return(-1);        vm_log(vm,"CONSOLE","console managed by NPE-G2 board\n");
2271          mv64460_sdma_bind_vtty(router->mv64460_sysctr,0,vm->vtty_con);
2272          mv64460_sdma_bind_vtty(router->mv64460_sysctr,1,vm->vtty_aux);
2273       }
2274    
2275     /* Show device list */     /* Show device list */
2276     c7200_show_hardware(router);     c7200_show_hardware(router);
2277     return(0);     return(0);
2278  }  }
2279    
2280  /* Boot the IOS image */  /* Boot the IOS image (MIPS) */
2281  int c7200_boot_ios(c7200_t *router)  static int c7200m_boot_ios(c7200_t *router)
2282  {    {  
2283     vm_instance_t *vm = router->vm;     vm_instance_t *vm = router->vm;
2284       cpu_mips_t *cpu;
2285    
2286     if (!vm->boot_cpu)     if (!vm->boot_cpu)
2287        return(-1);        return(-1);
# Line 2021  int c7200_boot_ios(c7200_t *router) Line 2296  int c7200_boot_ios(c7200_t *router)
2296     }     }
2297    
2298     /* Reset the boot CPU */     /* Reset the boot CPU */
2299     mips64_reset(vm->boot_cpu);     cpu = CPU_MIPS64(vm->boot_cpu);
2300       mips64_reset(cpu);
2301    
2302     /* Load IOS image */     /* Load IOS image */
2303     if (mips64_load_elf_image(vm->boot_cpu,vm->ios_image,     if (mips64_load_elf_image(cpu,vm->ios_image,
2304                               (vm->ghost_status == VM_GHOST_RAM_USE),                               (vm->ghost_status == VM_GHOST_RAM_USE),
2305                               &vm->ios_entry_point) < 0)                               &vm->ios_entry_point) < 0)
2306     {     {
# Line 2035  int c7200_boot_ios(c7200_t *router) Line 2311  int c7200_boot_ios(c7200_t *router)
2311     /* Launch the simulation */     /* Launch the simulation */
2312     printf("\nC7200 '%s': starting simulation (CPU0 PC=0x%llx), "     printf("\nC7200 '%s': starting simulation (CPU0 PC=0x%llx), "
2313            "JIT %sabled.\n",            "JIT %sabled.\n",
2314            vm->name,vm->boot_cpu->pc,vm->jit_use ? "en":"dis");            vm->name,cpu->pc,vm->jit_use ? "en":"dis");
2315    
2316     vm_log(vm,"C7200_BOOT",     vm_log(vm,"C7200_BOOT",
2317            "starting instance (CPU0 PC=0x%llx,idle_pc=0x%llx,JIT %s)\n",            "starting instance (CPU0 PC=0x%llx,idle_pc=0x%llx,JIT %s)\n",
2318            vm->boot_cpu->pc,vm->boot_cpu->idle_pc,vm->jit_use ? "on":"off");            cpu->pc,cpu->idle_pc,vm->jit_use ? "on":"off");
2319        
2320     /* Start main CPU */     /* Start main CPU */
2321     if (vm->ghost_status != VM_GHOST_RAM_GENERATE) {     if (vm->ghost_status != VM_GHOST_RAM_GENERATE) {
# Line 2051  int c7200_boot_ios(c7200_t *router) Line 2327  int c7200_boot_ios(c7200_t *router)
2327     return(0);     return(0);
2328  }  }
2329    
2330  /* Initialize a Cisco 7200 instance */  /* Boot the IOS image (PowerPC) */
2331  int c7200_init_instance(c7200_t *router)  static int c7200p_boot_ios(c7200_t *router)
2332    {  
2333       vm_instance_t *vm = router->vm;
2334       cpu_ppc_t *cpu;
2335    
2336       if (!vm->boot_cpu)
2337          return(-1);
2338    
2339       /* Suspend CPU activity since we will restart directly from ROM */
2340       vm_suspend(vm);
2341    
2342       /* Check that CPU activity is really suspended */
2343       if (cpu_group_sync_state(vm->cpu_group) == -1) {
2344          vm_error(vm,"unable to sync with system CPUs.\n");
2345          return(-1);
2346       }
2347    
2348       /* Reset the boot CPU */
2349       cpu = CPU_PPC32(vm->boot_cpu);
2350       ppc32_reset(cpu);
2351    
2352       /* Load IOS image */
2353       if (ppc32_load_elf_image(cpu,vm->ios_image,
2354                                (vm->ghost_status == VM_GHOST_RAM_USE),
2355                                &vm->ios_entry_point) < 0)
2356       {
2357          vm_error(vm,"failed to load Cisco IOS image '%s'.\n",vm->ios_image);
2358          return(-1);
2359       }
2360    
2361       /* Launch the simulation */
2362       printf("\nC7200P '%s': starting simulation (CPU0 IA=0x%8.8x), "
2363              "JIT %sabled.\n",
2364              vm->name,cpu->ia,vm->jit_use ? "en":"dis");
2365    
2366       vm_log(vm,"C7200P_BOOT",
2367              "starting instance (CPU0 IA=0x%8.8x,idle_pc=0x%8.8x,JIT %s)\n",
2368              cpu->ia,cpu->idle_pc,vm->jit_use ? "on":"off");
2369      
2370       /* Start main CPU */
2371       if (vm->ghost_status != VM_GHOST_RAM_GENERATE) {
2372          vm->status = VM_STATUS_RUNNING;
2373          cpu_start(vm->boot_cpu);
2374       } else {
2375          vm->status = VM_STATUS_SHUTDOWN;
2376       }
2377       return(0);
2378    }
2379    
2380    /* Set an IRQ */
2381    static void c7200m_set_irq(vm_instance_t *vm,u_int irq)
2382    {
2383       c7200_t *router = VM_C7200(vm);
2384       cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu);
2385       u_int slot,port;
2386    
2387       switch(irq) {
2388          case 0 ... 7:
2389             mips64_set_irq(cpu0,irq);
2390    
2391             if (cpu0->irq_idle_preempt[irq])
2392                cpu_idle_break_wait(cpu0->gen);
2393             break;
2394    
2395          case C7200_NETIO_IRQ_BASE ... C7200_NETIO_IRQ_END:
2396             c7200_net_irq_get_slot_port(irq,&slot,&port);
2397             dev_c7200_mpfpga_net_set_irq(router->mpfpga_data,slot,port);
2398             break;
2399       }
2400    }
2401    
2402    /* Clear an IRQ */
2403    static void c7200m_clear_irq(vm_instance_t *vm,u_int irq)
2404    {
2405       c7200_t *router = VM_C7200(vm);
2406       cpu_mips_t *cpu0 = CPU_MIPS64(vm->boot_cpu);
2407       u_int slot,port;
2408    
2409       switch(irq) {
2410          case 0 ... 7:
2411             mips64_clear_irq(cpu0,irq);
2412             break;
2413    
2414          case C7200_NETIO_IRQ_BASE ... C7200_NETIO_IRQ_END:
2415             c7200_net_irq_get_slot_port(irq,&slot,&port);
2416             dev_c7200_mpfpga_net_clear_irq(router->mpfpga_data,slot,port);
2417             break;
2418       }
2419    }
2420    
2421    /* Initialize a Cisco 7200 instance (MIPS) */
2422    static int c7200m_init_instance(c7200_t *router)
2423  {  {
2424     vm_instance_t *vm = router->vm;     vm_instance_t *vm = router->vm;
2425     m_uint32_t rom_entry_point;     m_uint32_t rom_entry_point;
2426     cpu_mips_t *cpu0;     cpu_mips_t *cpu0;
2427    
2428     /* Initialize the C7200 platform */     /* Initialize the C7200 platform */
2429     if (c7200_init_platform(router) == -1) {     if (c7200m_init_platform(router) == -1) {
2430        vm_error(vm,"unable to initialize the platform hardware.\n");        vm_error(vm,"unable to initialize the platform hardware.\n");
2431        return(-1);        return(-1);
2432     }     }
2433    
2434       /* IRQ routing */
2435       vm->set_irq = c7200m_set_irq;
2436       vm->clear_irq = c7200m_clear_irq;
2437    
2438     /* Load IOS configuration file */     /* Load IOS configuration file */
2439     if (vm->ios_config != NULL) {     if (vm->ios_config != NULL) {
2440        vm_nvram_push_config(vm,vm->ios_config);        vm_nvram_push_config(vm,vm->ios_config);
# Line 2071  int c7200_init_instance(c7200_t *router) Line 2442  int c7200_init_instance(c7200_t *router)
2442     }     }
2443    
2444     /* Load ROM (ELF image or embedded) */     /* Load ROM (ELF image or embedded) */
2445     cpu0 = vm->boot_cpu;     cpu0 = CPU_MIPS64(vm->boot_cpu);
2446     rom_entry_point = (m_uint32_t)MIPS_ROM_PC;     rom_entry_point = (m_uint32_t)MIPS_ROM_PC;
2447        
2448     if ((vm->rom_filename != NULL) &&     if ((vm->rom_filename != NULL) &&
# Line 2088  int c7200_init_instance(c7200_t *router) Line 2459  int c7200_init_instance(c7200_t *router)
2459        cpu0->sym_trace = 1;        cpu0->sym_trace = 1;
2460     }     }
2461    
2462     return(c7200_boot_ios(router));     return(c7200m_boot_ios(router));
2463    }
2464    
2465    /* Set an IRQ */
2466    static void c7200p_set_irq(vm_instance_t *vm,u_int irq)
2467    {
2468       c7200_t *router = VM_C7200(vm);
2469       cpu_ppc_t *cpu0 = CPU_PPC32(vm->boot_cpu);
2470       u_int slot,port;
2471    
2472       switch(irq) {
2473          case C7200_VTIMER_IRQ:
2474             ppc32_trigger_timer_irq(cpu0);
2475             break;
2476          case C7200_DUART_IRQ:
2477             dev_mv64460_set_gpp_intr(router->mv64460_sysctr,10);
2478             break;
2479          case C7200_NETIO_IRQ:
2480             dev_mv64460_set_gpp_intr(router->mv64460_sysctr,24);
2481             break;
2482          case C7200_PA_MGMT_IRQ:
2483             dev_mv64460_set_gpp_intr(router->mv64460_sysctr,20);
2484             break;
2485          case C7200_OIR_IRQ:
2486             dev_mv64460_set_gpp_intr(router->mv64460_sysctr,0);
2487             break;
2488          case C7200_NETIO_IRQ_BASE ... C7200_NETIO_IRQ_END:
2489             c7200_net_irq_get_slot_port(irq,&slot,&port);
2490             dev_c7200_mpfpga_net_set_irq(router->mpfpga_data,slot,port);
2491             break;
2492       }
2493    
2494       if (vm->irq_idle_preempt[irq])
2495          cpu_idle_break_wait(cpu0->gen);
2496    }
2497    
2498    /* Clear an IRQ */
2499    static void c7200p_clear_irq(vm_instance_t *vm,u_int irq)
2500    {
2501       c7200_t *router = VM_C7200(vm);
2502       u_int slot,port;
2503    
2504       switch(irq) {
2505          case C7200_DUART_IRQ:
2506             dev_mv64460_clear_gpp_intr(router->mv64460_sysctr,10);
2507             break;
2508          case C7200_NETIO_IRQ:
2509             dev_mv64460_clear_gpp_intr(router->mv64460_sysctr,24);
2510             break;
2511          case C7200_PA_MGMT_IRQ:
2512             dev_mv64460_clear_gpp_intr(router->mv64460_sysctr,20);
2513             break;
2514          case C7200_OIR_IRQ:
2515             dev_mv64460_clear_gpp_intr(router->mv64460_sysctr,0);
2516             break;
2517          case C7200_NETIO_IRQ_BASE ... C7200_NETIO_IRQ_END:
2518             c7200_net_irq_get_slot_port(irq,&slot,&port);
2519             dev_c7200_mpfpga_net_clear_irq(router->mpfpga_data,slot,port);
2520             break;
2521       }
2522    }
2523    
2524    /* Initialize a Cisco 7200 instance (PowerPC) */
2525    static int c7200p_init_instance(c7200_t *router)
2526    {
2527       vm_instance_t *vm = router->vm;
2528       m_uint32_t rom_entry_point;
2529       cpu_ppc_t *cpu0;
2530       int i;
2531    
2532       /* Initialize the C7200 platform */
2533       if (c7200p_init_platform(router) == -1) {
2534          vm_error(vm,"unable to initialize the platform hardware.\n");
2535          return(-1);
2536       }
2537    
2538       /* IRQ routing */
2539       vm->set_irq = c7200p_set_irq;
2540       vm->clear_irq = c7200p_clear_irq;
2541    
2542       /* Load ROM (ELF image or embedded) */
2543       cpu0 = CPU_PPC32(vm->boot_cpu);
2544       rom_entry_point = (m_uint32_t)PPC32_ROM_START;
2545    
2546       if ((vm->rom_filename != NULL) &&
2547           (ppc32_load_elf_image(cpu0,vm->rom_filename,0,&rom_entry_point) < 0))
2548       {
2549          vm_error(vm,"unable to load alternate ROM '%s', "
2550                   "fallback to embedded ROM.\n\n",vm->rom_filename);
2551          vm->rom_filename = NULL;
2552       }
2553    
2554       /* Initialize the MMU (TEST) */
2555       for(i=0;i<PPC32_SR_NR;i++)
2556          cpu0->sr[i] = i << 16;
2557    
2558       ppc32_set_sdr1(cpu0,((vm->ram_size - 2) * 1048576) + 0x1F);
2559       ppc32_init_page_table(cpu0);
2560       ppc32_map_zone(cpu0,cpu0->sr[C7200_G2_BOOTFLASH_ADDR >> 28],
2561                      C7200_G2_BOOTFLASH_ADDR,C7200_G2_BOOTFLASH_ADDR,
2562                      64*1048576,0,0x02);
2563    
2564       ppc32_map_zone(cpu0,cpu0->sr[0xD8000000 >> 28],
2565                      0xD8000000,0xD8000000,0x400000,0,0x02);
2566       ppc32_map_zone(cpu0,cpu0->sr[0xDC000000 >> 28],
2567                      0xDC000000,0xDC000000,0x400000,0,0x02);
2568    
2569       /* INST */
2570       cpu0->bat[PPC32_IBAT_IDX][0].reg[0] = 0x00003FFE;
2571       cpu0->bat[PPC32_IBAT_IDX][0].reg[1] = 0x00000003;
2572    
2573       cpu0->bat[PPC32_IBAT_IDX][3].reg[0] = 0xF0001FFE;
2574       cpu0->bat[PPC32_IBAT_IDX][3].reg[1] = 0xF0000003;
2575    
2576       /* DATA */
2577       cpu0->bat[PPC32_DBAT_IDX][0].reg[0] = 0x00003FFE;
2578       cpu0->bat[PPC32_DBAT_IDX][0].reg[1] = 0x00000003;
2579    
2580       cpu0->bat[PPC32_DBAT_IDX][3].reg[0] = 0xF0001FFE;
2581       cpu0->bat[PPC32_DBAT_IDX][3].reg[1] = 0xF0000003;
2582    
2583    
2584       return(c7200p_boot_ios(router));
2585    }
2586    
2587    /* Initialize a Cisco 7200 instance */
2588    int c7200_init_instance(c7200_t *router)
2589    {
2590       switch(router->npe_driver->npe_family) {
2591          case C7200_NPE_FAMILY_MIPS:
2592             return(c7200m_init_instance(router));
2593    
2594          case C7200_NPE_FAMILY_PPC:
2595             return(c7200p_init_instance(router));
2596            
2597          default:
2598             vm_error(router->vm,"unsupported NPE family %d",
2599                      router->npe_driver->npe_family);
2600             return(-1);
2601       }
2602  }  }
2603    
2604  /* Stop a Cisco 7200 instance */  /* Stop a Cisco 7200 instance */
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