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dpavlin |
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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2007 Christophe Fillot (cf@utc.fr) |
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* |
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* Generic Cisco C6k-SUP1 routines and definitions (EEPROM,...). |
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*/ |
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#ifndef __DEV_C6SUP1_H__ |
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#define __DEV_C6SUP1_H__ |
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#include <pthread.h> |
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#include "utils.h" |
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#include "net.h" |
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#include "device.h" |
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#include "pci_dev.h" |
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#include "nmc93cX6.h" |
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#include "net_io.h" |
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#include "vm.h" |
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/* Default MSFC1 parameters */ |
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#define C6SUP1_DEFAULT_RAM_SIZE 128 |
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#define C6SUP1_DEFAULT_ROM_SIZE 4 |
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#define C6SUP1_DEFAULT_NVRAM_SIZE 512 |
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#define C6SUP1_DEFAULT_CONF_REG 0x2102 |
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#define C6SUP1_DEFAULT_CLOCK_DIV 4 |
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#define C6SUP1_DEFAULT_RAM_MMAP 1 |
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/* EOBC + IBC */ |
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#define C6SUP1_MAX_PA_BAYS 2 |
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/* Maximum slots on 6513 */ |
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#define C6SUP1_MAX_SLOTS 13 |
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/* MSFC1 Timer IRQ (virtual) */ |
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#define C6SUP1_VTIMER_IRQ 0 |
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/* MSFC1 DUART Interrupt */ |
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#define C6SUP1_DUART_IRQ 5 |
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/* MSFC1 Network I/O Interrupt */ |
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#define C6SUP1_NETIO_IRQ 2 |
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/* MSFC1 PA Management Interrupt handler */ |
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#define C6SUP1_PA_MGMT_IRQ 3 |
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/* MSFC1 GT64k DMA/Timer Interrupt */ |
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#define C6SUP1_GT64K_IRQ 4 |
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/* MSFC1 Error/OIR Interrupt */ |
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#define C6SUP1_OIR_IRQ 6 |
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/* Network IRQ */ |
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#define C6SUP1_NETIO_IRQ_BASE 32 |
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#define C6SUP1_NETIO_IRQ_END \ |
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(C6SUP1_NETIO_IRQ_BASE + C6SUP1_MAX_PA_BAYS - 1) |
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/* MSFC1 base ram limit (256 Mb) */ |
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#define C6SUP1_BASE_RAM_LIMIT 256 |
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/* MSFC1 common device addresses */ |
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#define C6SUP1_GT64K_ADDR 0x14000000ULL |
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#define C6SUP1_GT64K_SEC_ADDR 0x15000000ULL |
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#define C6SUP1_BOOTFLASH_ADDR 0x1a000000ULL |
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#define C6SUP1_NVRAM_ADDR 0x1e000000ULL |
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#define C6SUP1_IOFPGA_ADDR 0x1e840000ULL |
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#define C6SUP1_MPFPGA_ADDR 0x1e880000ULL |
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#define C6SUP1_BITBUCKET_ADDR 0x1f000000ULL |
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#define C6SUP1_ROM_ADDR 0x1fc00000ULL |
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#define C6SUP1_IOMEM_ADDR 0x20000000ULL |
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#define C6SUP1_SRAM_ADDR 0x4b000000ULL |
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#define C6SUP1_BSWAP_ADDR 0xc0000000ULL |
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#define C6SUP1_PCI_IO_ADDR 0x100000000ULL |
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/* SRAM size */ |
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#define C6SUP1_SRAM_SIZE (4096*1024) |
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/* Reserved space for ROM in NVRAM */ |
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#define C6SUP1_NVRAM_ROM_RES_SIZE 2048 |
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/* MSFC1 physical address bus mask: keep only the lower 33 bits */ |
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#define C6SUP1_ADDR_BUS_MASK 0x1ffffffffULL |
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/* MSFC1 ELF Platform ID */ |
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#define C6SUP1_ELF_MACHINE_ID 0x19 |
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#define VM_C6SUP1(vm) ((c6sup1_t *)vm->hw_data) |
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/* MSFC1 router */ |
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typedef struct c6sup1_router c6sup1_t; |
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/* MSFC1 router */ |
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struct c6sup1_router { |
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/* Chassis MAC address */ |
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n_eth_addr_t mac_addr; |
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/* Associated VM instance */ |
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vm_instance_t *vm; |
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/* Midplane FPGA */ |
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struct c6sup1_mpfpga_data *mpfpga_data; |
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/* Slots EEPROM data */ |
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struct cisco_eeprom slot_eeprom[C6SUP1_MAX_SLOTS]; |
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/* Backplane, Supervisor and Slot EEPROM groups */ |
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struct nmc93cX6_group bp_eeprom_group; |
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struct nmc93cX6_group sup_eeprom_group; |
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struct nmc93cX6_group slot_eeprom_group; |
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/* Slot of this supervisor */ |
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u_int sup_slot; |
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}; |
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/* Initialize EEPROM groups */ |
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void c6sup1_init_eeprom_groups(c6sup1_t *router); |
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/* Get network IRQ for specified slot/port */ |
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u_int c6sup1_net_irq_for_slot_port(u_int slot,u_int port); |
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/* Show the list of available PA drivers */ |
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void c6sup1_pa_show_drivers(void); |
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/* Set chassis MAC address */ |
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int c6sup1_midplane_set_mac_addr(c6sup1_t *router,char *mac_addr); |
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/* Show MSFC1 hardware info */ |
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void c6sup1_show_hardware(c6sup1_t *router); |
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/* dev_c6sup1_iofpga_init() */ |
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int dev_c6sup1_iofpga_init(c6sup1_t *router,m_uint64_t paddr,m_uint32_t len); |
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/* dev_mpfpga_init() */ |
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int dev_c6sup1_mpfpga_init(c6sup1_t *router,m_uint64_t paddr,m_uint32_t len); |
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/* Register the c6sup1 platform */ |
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int c6sup1_platform_register(void); |
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#endif |
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