49 |
|
|
50 |
static struct net_irq_distrib net_irq_dist[C3725_MAX_NM_BAYS] = { |
static struct net_irq_distrib net_irq_dist[C3725_MAX_NM_BAYS] = { |
51 |
{ 0, 0 }, /* Slot 0: reg 0x26, 0x000000XX */ |
{ 0, 0 }, /* Slot 0: reg 0x26, 0x000000XX */ |
52 |
{ 1, 0 }, /* Slot 1: reg 0x28, 0x000000XX */ |
{ 1, 0 }, /* Slot 1: reg 0x28, 0x0000000X */ |
53 |
{ 1, 8 }, /* Slot 2: reg 0x28, 0x0000XX00 */ |
{ 1, 4 }, /* Slot 2: reg 0x28, 0x000000X0 */ |
54 |
}; |
}; |
55 |
|
|
56 |
/* IO FPGA structure */ |
/* IO FPGA structure */ |
64 |
|
|
65 |
/* Interrupt mask */ |
/* Interrupt mask */ |
66 |
m_uint16_t intr_mask; |
m_uint16_t intr_mask; |
67 |
|
|
68 |
|
/* WIC select */ |
69 |
|
u_int wic_select; |
70 |
|
u_int wic_cmd_pos; |
71 |
|
u_int wic_cmd_valid; |
72 |
|
m_uint16_t wic_cmd[2]; |
73 |
}; |
}; |
74 |
|
|
75 |
/* Mainboard EEPROM definition */ |
/* Mainboard EEPROM definition */ |
80 |
|
|
81 |
/* Mainboard EEPROM */ |
/* Mainboard EEPROM */ |
82 |
static const struct nmc93cX6_group eeprom_mb_group = { |
static const struct nmc93cX6_group eeprom_mb_group = { |
83 |
EEPROM_TYPE_NMC93C46, 1, 0, "Mainboard EEPROM", 0, { &eeprom_mb_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, |
84 |
|
EEPROM_DORD_NORMAL, |
85 |
|
EEPROM_DOUT_HIGH, |
86 |
|
EEPROM_DEBUG_DISABLED, |
87 |
|
"Mainboard EEPROM", |
88 |
|
{ &eeprom_mb_def }, |
89 |
}; |
}; |
90 |
|
|
91 |
/* NM EEPROM definition */ |
/* NM EEPROM definition */ |
96 |
|
|
97 |
/* NM EEPROM */ |
/* NM EEPROM */ |
98 |
static const struct nmc93cX6_group eeprom_nm_group = { |
static const struct nmc93cX6_group eeprom_nm_group = { |
99 |
EEPROM_TYPE_NMC93C46, 1, 0, "NM EEPROM", 0, { &eeprom_nm_def }, |
EEPROM_TYPE_NMC93C46, 1, 0, |
100 |
|
EEPROM_DORD_NORMAL, |
101 |
|
EEPROM_DOUT_HIGH, |
102 |
|
EEPROM_DEBUG_DISABLED, |
103 |
|
"NM EEPROM", |
104 |
|
{ &eeprom_nm_def }, |
105 |
}; |
}; |
106 |
|
|
107 |
/* Update network interrupt status */ |
/* Update network interrupt status */ |
144 |
dev_c3725_iofpga_net_update_irq(d); |
dev_c3725_iofpga_net_update_irq(d); |
145 |
} |
} |
146 |
|
|
147 |
|
/* Read a WIC EEPROM */ |
148 |
|
static m_uint16_t dev_c3725_read_wic_eeprom(struct c3725_iofpga_data *d) |
149 |
|
{ |
150 |
|
struct cisco_eeprom *eeprom; |
151 |
|
u_int wic_port; |
152 |
|
u_int eeprom_offset; |
153 |
|
m_uint8_t val[2]; |
154 |
|
|
155 |
|
switch(d->wic_select) { |
156 |
|
case 0x1700: |
157 |
|
wic_port = 0x10; |
158 |
|
break; |
159 |
|
case 0x1D00: |
160 |
|
wic_port = 0x20; |
161 |
|
break; |
162 |
|
case 0x3500: |
163 |
|
wic_port = 0x30; |
164 |
|
break; |
165 |
|
default: |
166 |
|
wic_port = 0; |
167 |
|
} |
168 |
|
|
169 |
|
/* No WIC in slot or no EEPROM: fake an empty EEPROM */ |
170 |
|
if (!wic_port || !(eeprom = vm_slot_get_eeprom(d->router->vm,0,wic_port))) |
171 |
|
return(0xFFFF); |
172 |
|
|
173 |
|
/* EEPROM offset is in the lowest 6 bits */ |
174 |
|
eeprom_offset = d->wic_cmd[0] & 0x3F; |
175 |
|
|
176 |
|
cisco_eeprom_get_byte(eeprom,eeprom_offset,&val[0]); |
177 |
|
cisco_eeprom_get_byte(eeprom,eeprom_offset+1,&val[1]); |
178 |
|
|
179 |
|
return(((m_uint16_t)val[0] << 8) | val[1]); |
180 |
|
} |
181 |
|
|
182 |
/* |
/* |
183 |
* dev_c3725_iofpga_access() |
* dev_c3725_iofpga_access() |
184 |
*/ |
*/ |
223 |
|
|
224 |
case 0x12: |
case 0x12: |
225 |
/* |
/* |
226 |
* Bit 0: 1=No WIC in slot 0 ? |
* Bit 0: 1=No WIC in slot 0. |
227 |
* Bit 1: 1=No WIC in slot 1 ? |
* Bit 1: 1=No WIC in slot 1. |
228 |
* Bit 2: 1=No WIC in slot 2 ? |
* Bit 2: 1=No WIC in slot 2. |
229 |
*/ |
*/ |
230 |
if (op_type == MTS_READ) |
if (op_type == MTS_READ) { |
231 |
*data = 0x0007; |
*data = 0xFFFF; |
232 |
|
|
233 |
|
/* check WIC 0 */ |
234 |
|
if (vm_slot_check_eeprom(d->router->vm,0,0x10)) |
235 |
|
*data &= ~0x01; |
236 |
|
|
237 |
|
/* check WIC 1 */ |
238 |
|
if (vm_slot_check_eeprom(d->router->vm,0,0x20)) |
239 |
|
*data &= ~0x02; |
240 |
|
|
241 |
|
/* check WIC 2 */ |
242 |
|
if (vm_slot_check_eeprom(d->router->vm,0,0x30)) |
243 |
|
*data &= ~0x04; |
244 |
|
} else { |
245 |
|
d->wic_select = *data; |
246 |
|
} |
247 |
break; |
break; |
248 |
|
|
249 |
case 0x14: |
case 0x14: |
264 |
|
|
265 |
/* WIC related: 16-bit data */ |
/* WIC related: 16-bit data */ |
266 |
case 0x42: |
case 0x42: |
267 |
|
if (op_type == MTS_READ) { |
268 |
|
if (d->wic_cmd_valid) { |
269 |
|
*data = dev_c3725_read_wic_eeprom(d); |
270 |
|
d->wic_cmd_valid = FALSE; |
271 |
|
} else { |
272 |
|
*data = 0xFFFF; |
273 |
|
} |
274 |
|
} else { |
275 |
|
/* |
276 |
|
* Store the EEPROM command (in 2 words). |
277 |
|
* |
278 |
|
* For a read, we have: |
279 |
|
* Word 0: 0x180 (nmc93c46 READ) + offset (6-bits). |
280 |
|
* Word 1: 0 (no data). |
281 |
|
*/ |
282 |
|
d->wic_cmd[d->wic_cmd_pos++] = *data; |
283 |
|
|
284 |
|
if (d->wic_cmd_pos == 2) { |
285 |
|
d->wic_cmd_pos = 0; |
286 |
|
d->wic_cmd_valid = TRUE; |
287 |
|
} |
288 |
|
} |
289 |
break; |
break; |
290 |
|
|
291 |
/* NM Slot 1 EEPROM */ |
/* NM Slot 1 EEPROM */ |
327 |
if (op_type == MTS_READ) { |
if (op_type == MTS_READ) { |
328 |
*data = 0xFFFF; |
*data = 0xFFFF; |
329 |
|
|
330 |
if (c3725_nm_check_eeprom(d->router,1)) |
if (vm_slot_get_card_ptr(d->router->vm,1)) |
331 |
*data &= ~0x0008; |
*data &= ~0x0008; |
332 |
|
|
333 |
if (c3725_nm_check_eeprom(d->router,2)) |
if (vm_slot_get_card_ptr(d->router->vm,2)) |
334 |
*data &= ~0x0800; |
*data &= ~0x0800; |
335 |
} |
} |
336 |
break; |
break; |
445 |
|
|
446 |
/* EEPROM for NM slot 1 */ |
/* EEPROM for NM slot 1 */ |
447 |
router->nm_eeprom_group[0] = eeprom_nm_group; |
router->nm_eeprom_group[0] = eeprom_nm_group; |
448 |
router->nm_eeprom_group[0].eeprom[0] = &router->nm_bay[1].eeprom; |
router->nm_eeprom_group[0].eeprom[0] = NULL; |
449 |
|
|
450 |
/* EEPROM for NM slot 2 */ |
/* EEPROM for NM slot 2 */ |
451 |
router->nm_eeprom_group[1] = eeprom_nm_group; |
router->nm_eeprom_group[1] = eeprom_nm_group; |
452 |
router->nm_eeprom_group[1].eeprom[0] = &router->nm_bay[2].eeprom; |
router->nm_eeprom_group[1].eeprom[0] = NULL; |
453 |
} |
} |
454 |
|
|
455 |
/* Shutdown the IO FPGA device */ |
/* Shutdown the IO FPGA device */ |