dynamips/trunk/cpu.h

/*
 * Cisco router simulation platform.
 * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
 */

#ifndef __CPU_H__
#define __CPU_H__

#include <pthread.h>
#include <setjmp.h>
#include "utils.h"
#include "jit_op.h"

#include "mips64.h"
#include "mips64_cp0.h"
#include "ppc32.h"

/* Possible CPU types */
enum {
   CPU_TYPE_MIPS64 = 1,
   CPU_TYPE_PPC32,
};

/* Virtual CPU states */
enum {
   CPU_STATE_RUNNING = 0,
   CPU_STATE_HALTED,
   CPU_STATE_SUSPENDED,
};

/* Maximum results for idle pc */
#define CPU_IDLE_PC_MAX_RES  10

/* Idle PC proposed value */
struct cpu_idle_pc {
   m_uint64_t pc;
   u_int count;
};

/* Number of recorded memory accesses (power of two) */
#define MEMLOG_COUNT   16

typedef struct memlog_access memlog_access_t;
struct memlog_access {
   m_uint64_t iaddr;
   m_uint64_t vaddr;
   m_uint64_t data;
   m_uint32_t data_valid;
   m_uint32_t op_size;
   m_uint32_t op_type;
};

/* Undefined memory access handler */
typedef int (*cpu_undefined_mem_handler_t)(cpu_gen_t *cpu,m_uint64_t vaddr,
                                           u_int op_size,u_int op_type,
                                           m_uint64_t *data);

/* Generic CPU definition */
struct cpu_gen {
   /* CPU type and identifier for MP systems */
   u_int type,id;

   /* CPU states */
   volatile u_int state,prev_state;
   volatile m_uint64_t seq_state;

   /* Thread running this CPU */
   pthread_t cpu_thread;
   int cpu_thread_running;

   /* Exception restore point */
   jmp_buf exec_loop_env;

   /* "Idle" loop management */
   u_int idle_count,idle_max,idle_sleep_time;
   pthread_mutex_t idle_mutex;
   pthread_cond_t idle_cond;

   /* VM instance */
   vm_instance_t *vm;

   /* Next CPU in group */
   cpu_gen_t *next;

   /* Idle PC proposal */
   struct cpu_idle_pc idle_pc_prop[CPU_IDLE_PC_MAX_RES];
   u_int idle_pc_prop_count;

   /* Specific CPU part */
   union {
      cpu_mips_t mips64_cpu;
      cpu_ppc_t ppc32_cpu;
   }sp;

   /* Methods */
   void (*reg_set)(cpu_gen_t *cpu,u_int reg_index,m_uint64_t val);
   void (*reg_dump)(cpu_gen_t *cpu);
   void (*mmu_dump)(cpu_gen_t *cpu);
   void (*mmu_raw_dump)(cpu_gen_t *cpu);
   void (*add_breakpoint)(cpu_gen_t *cpu,m_uint64_t addr);
   void (*remove_breakpoint)(cpu_gen_t *cpu,m_uint64_t addr);
   void (*set_idle_pc)(cpu_gen_t *cpu,m_uint64_t addr);
   void (*get_idling_pc)(cpu_gen_t *cpu);   
   void (*mts_rebuild)(cpu_gen_t *cpu);
   void (*mts_show_stats)(cpu_gen_t *cpu);

   cpu_undefined_mem_handler_t undef_mem_handler;

   /* Memory access log for fault debugging */
   u_int memlog_pos;
   memlog_access_t memlog_array[MEMLOG_COUNT];

   /* Statistics */
   m_uint64_t dev_access_counter;

   /* JIT op array for current compiled page */
   u_int jit_op_array_size;
   jit_op_t **jit_op_array;
   jit_op_t **jit_op_current;
   
   /* JIT op pool */
   jit_op_t *jit_op_pool[JIT_OP_POOL_NR];
};

/* CPU group definition */
typedef struct cpu_group cpu_group_t;
struct cpu_group {
   char *name;
   cpu_gen_t *cpu_list;
   void *priv_data;
};

#define CPU_MIPS64(cpu) (&(cpu)->sp.mips64_cpu)
#define CPU_PPC32(cpu)  (&(cpu)->sp.ppc32_cpu)

/* Get CPU instruction pointer */
static forced_inline m_uint64_t cpu_get_pc(cpu_gen_t *cpu)
{
   switch(cpu->type) {
      case CPU_TYPE_MIPS64:
         return(CPU_MIPS64(cpu)->pc);
      case CPU_TYPE_PPC32:
         return((m_uint64_t)CPU_PPC32(cpu)->ia);
      default:
         return(0);
   }
}

/* Get CPU performance counter */
static forced_inline m_uint32_t cpu_get_perf_counter(cpu_gen_t *cpu)
{
   switch(cpu->type) {
      case CPU_TYPE_MIPS64:
         return(CPU_MIPS64(cpu)->perf_counter);
      case CPU_TYPE_PPC32:
         return(CPU_PPC32(cpu)->perf_counter);
      default:
         return(0);
   }
}

/* Find a CPU in a group given its ID */
cpu_gen_t *cpu_group_find_id(cpu_group_t *group,u_int id);

/* Find the highest CPU ID in a CPU group */
int cpu_group_find_highest_id(cpu_group_t *group,u_int *highest_id);

/* Add a CPU in a CPU group */
int cpu_group_add(cpu_group_t *group,cpu_gen_t *cpu);

/* Create a new CPU group */
cpu_group_t *cpu_group_create(char *name);

/* Delete a CPU group */
void cpu_group_delete(cpu_group_t *group);

/* Rebuild the MTS subsystem for a CPU group */
int cpu_group_rebuild_mts(cpu_group_t *group);

/* Log a message for a CPU */
void cpu_log(cpu_gen_t *cpu,char *module,char *format,...);

/* Create a new CPU */
cpu_gen_t *cpu_create(vm_instance_t *vm,u_int type,u_int id);

/* Delete a CPU */
void cpu_delete(cpu_gen_t *cpu);

/* Start a CPU */
void cpu_start(cpu_gen_t *cpu);

/* Stop a CPU */
void cpu_stop(cpu_gen_t *cpu);

/* Start all CPUs of a CPU group */
void cpu_group_start_all_cpu(cpu_group_t *group);

/* Stop all CPUs of a CPU group */
void cpu_group_stop_all_cpu(cpu_group_t *group);

/* Set a state of all CPUs of a CPU group */
void cpu_group_set_state(cpu_group_t *group,u_int state);

/* Synchronize on CPUs (all CPUs must be inactive) */
int cpu_group_sync_state(cpu_group_t *group);

/* Save state of all CPUs */
int cpu_group_save_state(cpu_group_t *group);

/* Restore state of all CPUs */
int cpu_group_restore_state(cpu_group_t *group);

/* Virtual idle loop */
void cpu_idle_loop(cpu_gen_t *cpu);

/* Break idle wait state */
void cpu_idle_break_wait(cpu_gen_t *cpu);

/* Returns to the CPU exec loop */
static inline void cpu_exec_loop_enter(cpu_gen_t *cpu)
{
   longjmp(cpu->exec_loop_env,1);
}

/* Set the exec loop entry point */
#define cpu_exec_loop_set(cpu) setjmp((cpu)->exec_loop_env)

#endif
1	dpavlin	1	/*
2	dpavlin	7	* Cisco router simulation platform.
3	dpavlin	1	* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
4			*/
5
6			#ifndef __CPU_H__
7			#define __CPU_H__
8
9	dpavlin	7	#include <pthread.h>
10	dpavlin	11	#include <setjmp.h>
11	dpavlin	7	#include "utils.h"
12	dpavlin	9	#include "jit_op.h"
13	dpavlin	7
14	dpavlin	1	#include "mips64.h"
15	dpavlin	7	#include "mips64_cp0.h"
16			#include "ppc32.h"
17	dpavlin	1
18	dpavlin	7	/* Possible CPU types */
19			enum {
20			CPU_TYPE_MIPS64 = 1,
21			CPU_TYPE_PPC32,
22			};
23
24			/* Virtual CPU states */
25			enum {
26			CPU_STATE_RUNNING = 0,
27			CPU_STATE_HALTED,
28			CPU_STATE_SUSPENDED,
29			};
30
31			/* Maximum results for idle pc */
32			#define CPU_IDLE_PC_MAX_RES 10
33
34			/* Idle PC proposed value */
35			struct cpu_idle_pc {
36			m_uint64_t pc;
37			u_int count;
38			};
39
40			/* Number of recorded memory accesses (power of two) */
41			#define MEMLOG_COUNT 16
42
43			typedef struct memlog_access memlog_access_t;
44			struct memlog_access {
45			m_uint64_t iaddr;
46			m_uint64_t vaddr;
47			m_uint64_t data;
48			m_uint32_t data_valid;
49			m_uint32_t op_size;
50			m_uint32_t op_type;
51			};
52
53	dpavlin	11	/* Undefined memory access handler */
54			typedef int (cpu_undefined_mem_handler_t)(cpu_gen_t cpu,m_uint64_t vaddr,
55			u_int op_size,u_int op_type,
56			m_uint64_t *data);
57
58	dpavlin	7	/* Generic CPU definition */
59			struct cpu_gen {
60			/* CPU type and identifier for MP systems */
61			u_int type,id;
62
63			/* CPU states */
64			volatile u_int state,prev_state;
65			volatile m_uint64_t seq_state;
66
67			/* Thread running this CPU */
68			pthread_t cpu_thread;
69			int cpu_thread_running;
70
71	dpavlin	11	/* Exception restore point */
72			jmp_buf exec_loop_env;
73
74	dpavlin	7	/* "Idle" loop management */
75			u_int idle_count,idle_max,idle_sleep_time;
76			pthread_mutex_t idle_mutex;
77			pthread_cond_t idle_cond;
78
79			/* VM instance */
80			vm_instance_t *vm;
81
82			/* Next CPU in group */
83			cpu_gen_t *next;
84
85			/* Idle PC proposal */
86			struct cpu_idle_pc idle_pc_prop[CPU_IDLE_PC_MAX_RES];
87			u_int idle_pc_prop_count;
88
89			/* Specific CPU part */
90			union {
91			cpu_mips_t mips64_cpu;
92			cpu_ppc_t ppc32_cpu;
93			}sp;
94
95			/* Methods */
96			void (reg_set)(cpu_gen_t cpu,u_int reg_index,m_uint64_t val);
97			void (reg_dump)(cpu_gen_t cpu);
98			void (mmu_dump)(cpu_gen_t cpu);
99			void (mmu_raw_dump)(cpu_gen_t cpu);
100			void (add_breakpoint)(cpu_gen_t cpu,m_uint64_t addr);
101			void (remove_breakpoint)(cpu_gen_t cpu,m_uint64_t addr);
102			void (set_idle_pc)(cpu_gen_t cpu,m_uint64_t addr);
103			void (get_idling_pc)(cpu_gen_t cpu);
104			void (mts_rebuild)(cpu_gen_t cpu);
105			void (mts_show_stats)(cpu_gen_t cpu);
106
107	dpavlin	11	cpu_undefined_mem_handler_t undef_mem_handler;
108
109	dpavlin	7	/* Memory access log for fault debugging */
110			u_int memlog_pos;
111			memlog_access_t memlog_array[MEMLOG_COUNT];
112	dpavlin	8
113			/* Statistics */
114			m_uint64_t dev_access_counter;
115	dpavlin	9
116			/* JIT op array for current compiled page */
117			u_int jit_op_array_size;
118			jit_op_t **jit_op_array;
119			jit_op_t **jit_op_current;
120
121			/* JIT op pool */
122			jit_op_t *jit_op_pool[JIT_OP_POOL_NR];
123	dpavlin	7	};
124
125	dpavlin	1	/* CPU group definition */
126			typedef struct cpu_group cpu_group_t;
127			struct cpu_group {
128			char *name;
129	dpavlin	7	cpu_gen_t *cpu_list;
130	dpavlin	1	void *priv_data;
131			};
132
133	dpavlin	7	#define CPU_MIPS64(cpu) (&(cpu)->sp.mips64_cpu)
134			#define CPU_PPC32(cpu) (&(cpu)->sp.ppc32_cpu)
135
136			/* Get CPU instruction pointer */
137			static forced_inline m_uint64_t cpu_get_pc(cpu_gen_t *cpu)
138			{
139			switch(cpu->type) {
140			case CPU_TYPE_MIPS64:
141			return(CPU_MIPS64(cpu)->pc);
142			case CPU_TYPE_PPC32:
143			return((m_uint64_t)CPU_PPC32(cpu)->ia);
144			default:
145			return(0);
146			}
147			}
148
149			/* Get CPU performance counter */
150	dpavlin	11	static forced_inline m_uint32_t cpu_get_perf_counter(cpu_gen_t *cpu)
151	dpavlin	7	{
152			switch(cpu->type) {
153			case CPU_TYPE_MIPS64:
154			return(CPU_MIPS64(cpu)->perf_counter);
155			case CPU_TYPE_PPC32:
156			return(CPU_PPC32(cpu)->perf_counter);
157			default:
158			return(0);
159			}
160			}
161
162	dpavlin	1	/* Find a CPU in a group given its ID */
163	dpavlin	7	cpu_gen_t cpu_group_find_id(cpu_group_t group,u_int id);
164	dpavlin	1
165			/* Find the highest CPU ID in a CPU group */
166			int cpu_group_find_highest_id(cpu_group_t group,u_int highest_id);
167
168			/* Add a CPU in a CPU group */
169	dpavlin	7	int cpu_group_add(cpu_group_t group,cpu_gen_t cpu);
170	dpavlin	1
171			/* Create a new CPU group */
172			cpu_group_t cpu_group_create(char name);
173
174			/* Delete a CPU group */
175			void cpu_group_delete(cpu_group_t *group);
176
177			/* Rebuild the MTS subsystem for a CPU group */
178			int cpu_group_rebuild_mts(cpu_group_t *group);
179
180			/* Log a message for a CPU */
181	dpavlin	7	void cpu_log(cpu_gen_t cpu,char module,char *format,...);
182	dpavlin	1
183			/* Create a new CPU */
184	dpavlin	7	cpu_gen_t cpu_create(vm_instance_t vm,u_int type,u_int id);
185	dpavlin	1
186			/* Delete a CPU */
187	dpavlin	7	void cpu_delete(cpu_gen_t *cpu);
188	dpavlin	1
189			/* Start a CPU */
190	dpavlin	7	void cpu_start(cpu_gen_t *cpu);
191	dpavlin	1
192			/* Stop a CPU */
193	dpavlin	7	void cpu_stop(cpu_gen_t *cpu);
194	dpavlin	1
195			/* Start all CPUs of a CPU group */
196			void cpu_group_start_all_cpu(cpu_group_t *group);
197
198			/* Stop all CPUs of a CPU group */
199			void cpu_group_stop_all_cpu(cpu_group_t *group);
200
201			/* Set a state of all CPUs of a CPU group */
202			void cpu_group_set_state(cpu_group_t *group,u_int state);
203
204			/* Synchronize on CPUs (all CPUs must be inactive) */
205			int cpu_group_sync_state(cpu_group_t *group);
206
207			/* Save state of all CPUs */
208			int cpu_group_save_state(cpu_group_t *group);
209
210			/* Restore state of all CPUs */
211			int cpu_group_restore_state(cpu_group_t *group);
212
213	dpavlin	7	/* Virtual idle loop */
214			void cpu_idle_loop(cpu_gen_t *cpu);
215
216			/* Break idle wait state */
217			void cpu_idle_break_wait(cpu_gen_t *cpu);
218
219	dpavlin	11	/* Returns to the CPU exec loop */
220			static inline void cpu_exec_loop_enter(cpu_gen_t *cpu)
221			{
222			longjmp(cpu->exec_loop_env,1);
223			}
224
225			/* Set the exec loop entry point */
226			#define cpu_exec_loop_set(cpu) setjmp((cpu)->exec_loop_env)
227
228	dpavlin	1	#endif