/[VRac]/Z80/src/CodesXCB.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /Z80/src/CodesXCB.h

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Revision 111 - (show annotations)
Fri Aug 3 12:50:08 2007 UTC (16 years, 8 months ago) by dpavlin
File MIME type: text/plain
File size: 3353 byte(s)
import upstream Z80-010807
1 /** Z80: portable Z80 emulator *******************************/
2 /** **/
3 /** CodesXCB.h **/
4 /** **/
5 /** This file contains implementation for FD/DD-CB tables **/
6 /** of Z80 commands. It is included from Z80.c. **/
7 /** **/
8 /** Copyright (C) Marat Fayzullin 1994-2007 **/
9 /** You are not allowed to distribute this software **/
10 /** commercially. Please, notify me, if you make any **/
11 /** changes to this file. **/
12 /*************************************************************/
13
14 case RLC_xHL: I=RdZ80(J.W);M_RLC(I);WrZ80(J.W,I);break;
15 case RRC_xHL: I=RdZ80(J.W);M_RRC(I);WrZ80(J.W,I);break;
16 case RL_xHL: I=RdZ80(J.W);M_RL(I);WrZ80(J.W,I);break;
17 case RR_xHL: I=RdZ80(J.W);M_RR(I);WrZ80(J.W,I);break;
18 case SLA_xHL: I=RdZ80(J.W);M_SLA(I);WrZ80(J.W,I);break;
19 case SRA_xHL: I=RdZ80(J.W);M_SRA(I);WrZ80(J.W,I);break;
20 case SLL_xHL: I=RdZ80(J.W);M_SLL(I);WrZ80(J.W,I);break;
21 case SRL_xHL: I=RdZ80(J.W);M_SRL(I);WrZ80(J.W,I);break;
22
23 case BIT0_B: case BIT0_C: case BIT0_D: case BIT0_E:
24 case BIT0_H: case BIT0_L: case BIT0_A:
25 case BIT0_xHL: I=RdZ80(J.W);M_BIT(0,I);break;
26 case BIT1_B: case BIT1_C: case BIT1_D: case BIT1_E:
27 case BIT1_H: case BIT1_L: case BIT1_A:
28 case BIT1_xHL: I=RdZ80(J.W);M_BIT(1,I);break;
29 case BIT2_B: case BIT2_C: case BIT2_D: case BIT2_E:
30 case BIT2_H: case BIT2_L: case BIT2_A:
31 case BIT2_xHL: I=RdZ80(J.W);M_BIT(2,I);break;
32 case BIT3_B: case BIT3_C: case BIT3_D: case BIT3_E:
33 case BIT3_H: case BIT3_L: case BIT3_A:
34 case BIT3_xHL: I=RdZ80(J.W);M_BIT(3,I);break;
35 case BIT4_B: case BIT4_C: case BIT4_D: case BIT4_E:
36 case BIT4_H: case BIT4_L: case BIT4_A:
37 case BIT4_xHL: I=RdZ80(J.W);M_BIT(4,I);break;
38 case BIT5_B: case BIT5_C: case BIT5_D: case BIT5_E:
39 case BIT5_H: case BIT5_L: case BIT5_A:
40 case BIT5_xHL: I=RdZ80(J.W);M_BIT(5,I);break;
41 case BIT6_B: case BIT6_C: case BIT6_D: case BIT6_E:
42 case BIT6_H: case BIT6_L: case BIT6_A:
43 case BIT6_xHL: I=RdZ80(J.W);M_BIT(6,I);break;
44 case BIT7_B: case BIT7_C: case BIT7_D: case BIT7_E:
45 case BIT7_H: case BIT7_L: case BIT7_A:
46 case BIT7_xHL: I=RdZ80(J.W);M_BIT(7,I);break;
47
48 case RES0_xHL: I=RdZ80(J.W);M_RES(0,I);WrZ80(J.W,I);break;
49 case RES1_xHL: I=RdZ80(J.W);M_RES(1,I);WrZ80(J.W,I);break;
50 case RES2_xHL: I=RdZ80(J.W);M_RES(2,I);WrZ80(J.W,I);break;
51 case RES3_xHL: I=RdZ80(J.W);M_RES(3,I);WrZ80(J.W,I);break;
52 case RES4_xHL: I=RdZ80(J.W);M_RES(4,I);WrZ80(J.W,I);break;
53 case RES5_xHL: I=RdZ80(J.W);M_RES(5,I);WrZ80(J.W,I);break;
54 case RES6_xHL: I=RdZ80(J.W);M_RES(6,I);WrZ80(J.W,I);break;
55 case RES7_xHL: I=RdZ80(J.W);M_RES(7,I);WrZ80(J.W,I);break;
56
57 case SET0_xHL: I=RdZ80(J.W);M_SET(0,I);WrZ80(J.W,I);break;
58 case SET1_xHL: I=RdZ80(J.W);M_SET(1,I);WrZ80(J.W,I);break;
59 case SET2_xHL: I=RdZ80(J.W);M_SET(2,I);WrZ80(J.W,I);break;
60 case SET3_xHL: I=RdZ80(J.W);M_SET(3,I);WrZ80(J.W,I);break;
61 case SET4_xHL: I=RdZ80(J.W);M_SET(4,I);WrZ80(J.W,I);break;
62 case SET5_xHL: I=RdZ80(J.W);M_SET(5,I);WrZ80(J.W,I);break;
63 case SET6_xHL: I=RdZ80(J.W);M_SET(6,I);WrZ80(J.W,I);break;
64 case SET7_xHL: I=RdZ80(J.W);M_SET(7,I);WrZ80(J.W,I);break;

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